SYSTEMS AND METHODS FOR CODE GENERATION FOR A PLURALITY OF ARCHITECTURES

Systems and methods for code generation for a plurality of architectures. At a host architecture, a JIT compile operation is performed for a received JavaScript or Web Assembly file. The JIT compiler references a host library that has been updated to include at least one new JIT instruction. Output...

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Hauptverfasser:	Poornachandran, Rajesh, Sun, Mingqiu, Selvaraje, Gopinatth, Zimmer, Vincent
Format:	Patent
Sprache:	eng
Schlagworte:	CALCULATING COMPUTING COUNTING ELECTRIC DIGITAL DATA PROCESSING PHYSICS
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creator	Poornachandran, Rajesh Sun, Mingqiu Selvaraje, Gopinatth Zimmer, Vincent
description	Systems and methods for code generation for a plurality of architectures. At a host architecture, a JIT compile operation is performed for a received JavaScript or Web Assembly file. The JIT compiler references a host library that has been updated to include at least one new JIT instruction. Output from the JIT compile operation is compiled machine code for the host architecture that has new opcodes (OPX) added, responsive to the new JIT instruction. The JIT compiler executes the opcodes (OPX) in XuCode mode, meaning that the host architecture switches into a hardware protected private ISA (Instruction Set Architecture) called XuCode to implement the new JIT opcode instruction in XuCode.
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fullrecord	<record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_US2023018149A1</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>US2023018149A1</sourcerecordid><originalsourceid>FETCH-epo_espacenet_US2023018149A13</originalsourceid><addsrcrecordid>eNrjZPAIjgwOcfUNVnD0c1HwdQ3x8HcJVnDzD1Jw9ndxVXB39XMNcgzx9PcDizkqBPiEBjn6eIZEKvi7KTgGOXt4hrg6h4QGuQbzMLCmJeYUp_JCaW4GZTfXEGcP3dSC_PjU4oLE5NS81JL40GAjAyNjA0MLQxNLR0Nj4lQBALXyLcU</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>SYSTEMS AND METHODS FOR CODE GENERATION FOR A PLURALITY OF ARCHITECTURES</title><source>esp@cenet</source><creator>Poornachandran, Rajesh ; Sun, Mingqiu ; Selvaraje, Gopinatth ; Zimmer, Vincent</creator><creatorcontrib>Poornachandran, Rajesh ; Sun, Mingqiu ; Selvaraje, Gopinatth ; Zimmer, Vincent</creatorcontrib><description>Systems and methods for code generation for a plurality of architectures. At a host architecture, a JIT compile operation is performed for a received JavaScript or Web Assembly file. The JIT compiler references a host library that has been updated to include at least one new JIT instruction. Output from the JIT compile operation is compiled machine code for the host architecture that has new opcodes (OPX) added, responsive to the new JIT instruction. The JIT compiler executes the opcodes (OPX) in XuCode mode, meaning that the host architecture switches into a hardware protected private ISA (Instruction Set Architecture) called XuCode to implement the new JIT opcode instruction in XuCode.</description><language>eng</language><subject>CALCULATING ; COMPUTING ; COUNTING ; ELECTRIC DIGITAL DATA PROCESSING ; PHYSICS</subject><creationdate>2023</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20230119&DB=EPODOC&CC=US&NR=2023018149A1$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,777,882,25545,76296</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20230119&DB=EPODOC&CC=US&NR=2023018149A1$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>Poornachandran, Rajesh</creatorcontrib><creatorcontrib>Sun, Mingqiu</creatorcontrib><creatorcontrib>Selvaraje, Gopinatth</creatorcontrib><creatorcontrib>Zimmer, Vincent</creatorcontrib><title>SYSTEMS AND METHODS FOR CODE GENERATION FOR A PLURALITY OF ARCHITECTURES</title><description>Systems and methods for code generation for a plurality of architectures. At a host architecture, a JIT compile operation is performed for a received JavaScript or Web Assembly file. The JIT compiler references a host library that has been updated to include at least one new JIT instruction. Output from the JIT compile operation is compiled machine code for the host architecture that has new opcodes (OPX) added, responsive to the new JIT instruction. The JIT compiler executes the opcodes (OPX) in XuCode mode, meaning that the host architecture switches into a hardware protected private ISA (Instruction Set Architecture) called XuCode to implement the new JIT opcode instruction in XuCode.</description><subject>CALCULATING</subject><subject>COMPUTING</subject><subject>COUNTING</subject><subject>ELECTRIC DIGITAL DATA PROCESSING</subject><subject>PHYSICS</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2023</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZPAIjgwOcfUNVnD0c1HwdQ3x8HcJVnDzD1Jw9ndxVXB39XMNcgzx9PcDizkqBPiEBjn6eIZEKvi7KTgGOXt4hrg6h4QGuQbzMLCmJeYUp_JCaW4GZTfXEGcP3dSC_PjU4oLE5NS81JL40GAjAyNjA0MLQxNLR0Nj4lQBALXyLcU</recordid><startdate>20230119</startdate><enddate>20230119</enddate><creator>Poornachandran, Rajesh</creator><creator>Sun, Mingqiu</creator><creator>Selvaraje, Gopinatth</creator><creator>Zimmer, Vincent</creator><scope>EVB</scope></search><sort><creationdate>20230119</creationdate><title>SYSTEMS AND METHODS FOR CODE GENERATION FOR A PLURALITY OF ARCHITECTURES</title><author>Poornachandran, Rajesh ; Sun, Mingqiu ; Selvaraje, Gopinatth ; Zimmer, Vincent</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_US2023018149A13</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>2023</creationdate><topic>CALCULATING</topic><topic>COMPUTING</topic><topic>COUNTING</topic><topic>ELECTRIC DIGITAL DATA PROCESSING</topic><topic>PHYSICS</topic><toplevel>online_resources</toplevel><creatorcontrib>Poornachandran, Rajesh</creatorcontrib><creatorcontrib>Sun, Mingqiu</creatorcontrib><creatorcontrib>Selvaraje, Gopinatth</creatorcontrib><creatorcontrib>Zimmer, Vincent</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Poornachandran, Rajesh</au><au>Sun, Mingqiu</au><au>Selvaraje, Gopinatth</au><au>Zimmer, Vincent</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>SYSTEMS AND METHODS FOR CODE GENERATION FOR A PLURALITY OF ARCHITECTURES</title><date>2023-01-19</date><risdate>2023</risdate><abstract>Systems and methods for code generation for a plurality of architectures. At a host architecture, a JIT compile operation is performed for a received JavaScript or Web Assembly file. The JIT compiler references a host library that has been updated to include at least one new JIT instruction. Output from the JIT compile operation is compiled machine code for the host architecture that has new opcodes (OPX) added, responsive to the new JIT instruction. The JIT compiler executes the opcodes (OPX) in XuCode mode, meaning that the host architecture switches into a hardware protected private ISA (Instruction Set Architecture) called XuCode to implement the new JIT opcode instruction in XuCode.</abstract><oa>free_for_read</oa></addata></record>
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title	SYSTEMS AND METHODS FOR CODE GENERATION FOR A PLURALITY OF ARCHITECTURES
url	https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-01-18T17%3A14%3A39IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-epo_EVB&rft_val_fmt=info:ofi/fmt:kev:mtx:patent&rft.genre=patent&rft.au=Poornachandran,%20Rajesh&rft.date=2023-01-19&rft_id=info:doi/&rft_dat=%3Cepo_EVB%3EUS2023018149A1%3C/epo_EVB%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rfr_iscdi=true