3DIC STRUCTURE FOR HIGH VOLTAGE DEVICE ON A SOI SUBSTRATE
In some embodiments, the present disclosure relates to a device that includes a silicon-on-insulator (SOI) substrate. A first semiconductor device is disposed on a frontside of the SOI substrate. An interconnect structure is arranged over the frontside of the SOI substrate and coupled to the first s...
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| creator | Chuang, Harry-Hak-Lay Lin, Hsin Fu Wu, Wei Cheng Huang, Wen-Tuo |
| description | In some embodiments, the present disclosure relates to a device that includes a silicon-on-insulator (SOI) substrate. A first semiconductor device is disposed on a frontside of the SOI substrate. An interconnect structure is arranged over the frontside of the SOI substrate and coupled to the first semiconductor device. A shallow trench isolation (STI) structure is arranged within the frontside of the SOI substrate and surrounds the first semiconductor device. First and second deep trench isolation (DTI) structures extend from the STI structure to an insulator layer of the SOI substrate. Portions of the first and second DTI structures are spaced apart from one another by an active layer of the SOI substrate. A backside through substrate via (BTSV) extends completely through the SOI substrate from a backside to the frontside of the SOI substrate. The BTSV is arranged directly between the first and second DTI structures. |
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| fullrecord | <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_US2022415930A1</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>US2022415930A1</sourcerecordid><originalsourceid>FETCH-epo_espacenet_US2022415930A13</originalsourceid><addsrcrecordid>eNrjZLA0dvF0VggOCQp1DgkNclVw8w9S8PB091AI8_cJcXR3VXBxDfN0dlXw91NwVAj291QIDnUCqnYMceVhYE1LzClO5YXS3AzKbq4hzh66qQX58anFBYnJqXmpJfGhwUYGRkYmhqaWxgaOhsbEqQIABDApTw</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>3DIC STRUCTURE FOR HIGH VOLTAGE DEVICE ON A SOI SUBSTRATE</title><source>esp@cenet</source><creator>Chuang, Harry-Hak-Lay ; Lin, Hsin Fu ; Wu, Wei Cheng ; Huang, Wen-Tuo</creator><creatorcontrib>Chuang, Harry-Hak-Lay ; Lin, Hsin Fu ; Wu, Wei Cheng ; Huang, Wen-Tuo</creatorcontrib><description>In some embodiments, the present disclosure relates to a device that includes a silicon-on-insulator (SOI) substrate. A first semiconductor device is disposed on a frontside of the SOI substrate. An interconnect structure is arranged over the frontside of the SOI substrate and coupled to the first semiconductor device. A shallow trench isolation (STI) structure is arranged within the frontside of the SOI substrate and surrounds the first semiconductor device. First and second deep trench isolation (DTI) structures extend from the STI structure to an insulator layer of the SOI substrate. Portions of the first and second DTI structures are spaced apart from one another by an active layer of the SOI substrate. A backside through substrate via (BTSV) extends completely through the SOI substrate from a backside to the frontside of the SOI substrate. The BTSV is arranged directly between the first and second DTI structures.</description><language>eng</language><subject>BASIC ELECTRIC ELEMENTS ; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ; ELECTRICITY ; SEMICONDUCTOR DEVICES</subject><creationdate>2022</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20221229&DB=EPODOC&CC=US&NR=2022415930A1$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,778,883,25547,76298</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20221229&DB=EPODOC&CC=US&NR=2022415930A1$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>Chuang, Harry-Hak-Lay</creatorcontrib><creatorcontrib>Lin, Hsin Fu</creatorcontrib><creatorcontrib>Wu, Wei Cheng</creatorcontrib><creatorcontrib>Huang, Wen-Tuo</creatorcontrib><title>3DIC STRUCTURE FOR HIGH VOLTAGE DEVICE ON A SOI SUBSTRATE</title><description>In some embodiments, the present disclosure relates to a device that includes a silicon-on-insulator (SOI) substrate. A first semiconductor device is disposed on a frontside of the SOI substrate. An interconnect structure is arranged over the frontside of the SOI substrate and coupled to the first semiconductor device. A shallow trench isolation (STI) structure is arranged within the frontside of the SOI substrate and surrounds the first semiconductor device. First and second deep trench isolation (DTI) structures extend from the STI structure to an insulator layer of the SOI substrate. Portions of the first and second DTI structures are spaced apart from one another by an active layer of the SOI substrate. A backside through substrate via (BTSV) extends completely through the SOI substrate from a backside to the frontside of the SOI substrate. The BTSV is arranged directly between the first and second DTI structures.</description><subject>BASIC ELECTRIC ELEMENTS</subject><subject>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</subject><subject>ELECTRICITY</subject><subject>SEMICONDUCTOR DEVICES</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2022</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZLA0dvF0VggOCQp1DgkNclVw8w9S8PB091AI8_cJcXR3VXBxDfN0dlXw91NwVAj291QIDnUCqnYMceVhYE1LzClO5YXS3AzKbq4hzh66qQX58anFBYnJqXmpJfGhwUYGRkYmhqaWxgaOhsbEqQIABDApTw</recordid><startdate>20221229</startdate><enddate>20221229</enddate><creator>Chuang, Harry-Hak-Lay</creator><creator>Lin, Hsin Fu</creator><creator>Wu, Wei Cheng</creator><creator>Huang, Wen-Tuo</creator><scope>EVB</scope></search><sort><creationdate>20221229</creationdate><title>3DIC STRUCTURE FOR HIGH VOLTAGE DEVICE ON A SOI SUBSTRATE</title><author>Chuang, Harry-Hak-Lay ; Lin, Hsin Fu ; Wu, Wei Cheng ; Huang, Wen-Tuo</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_US2022415930A13</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>2022</creationdate><topic>BASIC ELECTRIC ELEMENTS</topic><topic>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</topic><topic>ELECTRICITY</topic><topic>SEMICONDUCTOR DEVICES</topic><toplevel>online_resources</toplevel><creatorcontrib>Chuang, Harry-Hak-Lay</creatorcontrib><creatorcontrib>Lin, Hsin Fu</creatorcontrib><creatorcontrib>Wu, Wei Cheng</creatorcontrib><creatorcontrib>Huang, Wen-Tuo</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Chuang, Harry-Hak-Lay</au><au>Lin, Hsin Fu</au><au>Wu, Wei Cheng</au><au>Huang, Wen-Tuo</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>3DIC STRUCTURE FOR HIGH VOLTAGE DEVICE ON A SOI SUBSTRATE</title><date>2022-12-29</date><risdate>2022</risdate><abstract>In some embodiments, the present disclosure relates to a device that includes a silicon-on-insulator (SOI) substrate. A first semiconductor device is disposed on a frontside of the SOI substrate. An interconnect structure is arranged over the frontside of the SOI substrate and coupled to the first semiconductor device. A shallow trench isolation (STI) structure is arranged within the frontside of the SOI substrate and surrounds the first semiconductor device. First and second deep trench isolation (DTI) structures extend from the STI structure to an insulator layer of the SOI substrate. Portions of the first and second DTI structures are spaced apart from one another by an active layer of the SOI substrate. A backside through substrate via (BTSV) extends completely through the SOI substrate from a backside to the frontside of the SOI substrate. The BTSV is arranged directly between the first and second DTI structures.</abstract><oa>free_for_read</oa></addata></record> |
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| subjects | BASIC ELECTRIC ELEMENTS ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ELECTRICITY SEMICONDUCTOR DEVICES |
| title | 3DIC STRUCTURE FOR HIGH VOLTAGE DEVICE ON A SOI SUBSTRATE |
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