METHOD TO IMPROVE DATA RETENTION OF NON-VOLATILE MEMORY IN LOGIC PROCESSES

In some embodiments, the present disclosure relates to an integrated chip (IC), including a substrate, a floating gate electrode disposed over the substrate, a contact etch stop layer (CESL) structure disposed over the floating gate electrode, an insulating stack separating the floating gate electro...

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Hauptverfasser:	Tsui, Ying Kit Felix, Chen, Shih-Hsien, Lo, Wen-Shun, Wu, Tai-Yi
Format:	Patent
Sprache:	eng
Schlagworte:	ELECTRICITY
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creator	Tsui, Ying Kit Felix Chen, Shih-Hsien Lo, Wen-Shun Wu, Tai-Yi
description	In some embodiments, the present disclosure relates to an integrated chip (IC), including a substrate, a floating gate electrode disposed over the substrate, a contact etch stop layer (CESL) structure disposed over the floating gate electrode, an insulating stack separating the floating gate electrode from the CESL structure, the insulating stack including a first resist protective layer disposed over the floating gate electrode, a second resist protective layer disposed over the first resist protective layer, and an insulating layer separating the first resist protective layer from the second resist protective layer.
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fullrecord	<record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_US2022415914A1</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>US2022415914A1</sourcerecordid><originalsourceid>FETCH-epo_espacenet_US2022415914A13</originalsourceid><addsrcrecordid>eNrjZPDydQ3x8HdRCPFX8PQNCPIPc1VwcQxxVAhyDXH1C_H091Pwd1Pw8_fTDfP3cQzx9HFV8HX19Q-KVPD0U_Dxd_d0VgBqcnYNDnYN5mFgTUvMKU7lhdLcDMpuriHOHrqpBfnxqcUFicmpeakl8aHBRgZGRiaGppaGJo6GxsSpAgAXGS5b</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>METHOD TO IMPROVE DATA RETENTION OF NON-VOLATILE MEMORY IN LOGIC PROCESSES</title><source>esp@cenet</source><creator>Tsui, Ying Kit Felix ; Chen, Shih-Hsien ; Lo, Wen-Shun ; Wu, Tai-Yi</creator><creatorcontrib>Tsui, Ying Kit Felix ; Chen, Shih-Hsien ; Lo, Wen-Shun ; Wu, Tai-Yi</creatorcontrib><description>In some embodiments, the present disclosure relates to an integrated chip (IC), including a substrate, a floating gate electrode disposed over the substrate, a contact etch stop layer (CESL) structure disposed over the floating gate electrode, an insulating stack separating the floating gate electrode from the CESL structure, the insulating stack including a first resist protective layer disposed over the floating gate electrode, a second resist protective layer disposed over the first resist protective layer, and an insulating layer separating the first resist protective layer from the second resist protective layer.</description><language>eng</language><subject>ELECTRICITY</subject><creationdate>2022</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20221229&DB=EPODOC&CC=US&NR=2022415914A1$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,777,882,25545,76296</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20221229&DB=EPODOC&CC=US&NR=2022415914A1$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>Tsui, Ying Kit Felix</creatorcontrib><creatorcontrib>Chen, Shih-Hsien</creatorcontrib><creatorcontrib>Lo, Wen-Shun</creatorcontrib><creatorcontrib>Wu, Tai-Yi</creatorcontrib><title>METHOD TO IMPROVE DATA RETENTION OF NON-VOLATILE MEMORY IN LOGIC PROCESSES</title><description>In some embodiments, the present disclosure relates to an integrated chip (IC), including a substrate, a floating gate electrode disposed over the substrate, a contact etch stop layer (CESL) structure disposed over the floating gate electrode, an insulating stack separating the floating gate electrode from the CESL structure, the insulating stack including a first resist protective layer disposed over the floating gate electrode, a second resist protective layer disposed over the first resist protective layer, and an insulating layer separating the first resist protective layer from the second resist protective layer.</description><subject>ELECTRICITY</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2022</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZPDydQ3x8HdRCPFX8PQNCPIPc1VwcQxxVAhyDXH1C_H091Pwd1Pw8_fTDfP3cQzx9HFV8HX19Q-KVPD0U_Dxd_d0VgBqcnYNDnYN5mFgTUvMKU7lhdLcDMpuriHOHrqpBfnxqcUFicmpeakl8aHBRgZGRiaGppaGJo6GxsSpAgAXGS5b</recordid><startdate>20221229</startdate><enddate>20221229</enddate><creator>Tsui, Ying Kit Felix</creator><creator>Chen, Shih-Hsien</creator><creator>Lo, Wen-Shun</creator><creator>Wu, Tai-Yi</creator><scope>EVB</scope></search><sort><creationdate>20221229</creationdate><title>METHOD TO IMPROVE DATA RETENTION OF NON-VOLATILE MEMORY IN LOGIC PROCESSES</title><author>Tsui, Ying Kit Felix ; Chen, Shih-Hsien ; Lo, Wen-Shun ; Wu, Tai-Yi</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_US2022415914A13</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>2022</creationdate><topic>ELECTRICITY</topic><toplevel>online_resources</toplevel><creatorcontrib>Tsui, Ying Kit Felix</creatorcontrib><creatorcontrib>Chen, Shih-Hsien</creatorcontrib><creatorcontrib>Lo, Wen-Shun</creatorcontrib><creatorcontrib>Wu, Tai-Yi</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Tsui, Ying Kit Felix</au><au>Chen, Shih-Hsien</au><au>Lo, Wen-Shun</au><au>Wu, Tai-Yi</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>METHOD TO IMPROVE DATA RETENTION OF NON-VOLATILE MEMORY IN LOGIC PROCESSES</title><date>2022-12-29</date><risdate>2022</risdate><abstract>In some embodiments, the present disclosure relates to an integrated chip (IC), including a substrate, a floating gate electrode disposed over the substrate, a contact etch stop layer (CESL) structure disposed over the floating gate electrode, an insulating stack separating the floating gate electrode from the CESL structure, the insulating stack including a first resist protective layer disposed over the floating gate electrode, a second resist protective layer disposed over the first resist protective layer, and an insulating layer separating the first resist protective layer from the second resist protective layer.</abstract><oa>free_for_read</oa></addata></record>
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title	METHOD TO IMPROVE DATA RETENTION OF NON-VOLATILE MEMORY IN LOGIC PROCESSES
url	https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-01-20T13%3A16%3A58IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-epo_EVB&rft_val_fmt=info:ofi/fmt:kev:mtx:patent&rft.genre=patent&rft.au=Tsui,%20Ying%20Kit%20Felix&rft.date=2022-12-29&rft_id=info:doi/&rft_dat=%3Cepo_EVB%3EUS2022415914A1%3C/epo_EVB%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rfr_iscdi=true