THREE-DIMENSIONAL MEMORY DEVICE CONTAINING SELF-ALIGNED BIT LINE CONTACTS AND METHODS FOR FORMING THE SAME

A vertical layer stack including a bit-line-level dielectric layer and an etch stop dielectric layer can be formed over an array region. Bit-line trenches are formed through the vertical layer stack. Bit-line-trench fill structures are formed in the bit-line trenches. Each of the bit-line-trench fil...

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Bibliographische Detailangaben

Hauptverfasser:	AMANO, Fumitaka, ISHIKAWA, Kensuke, MIYAMOTO, Masato, OSAWA, Yusuke, MUSHIGA, Mitsuteru, YADA, Shinsuke, KASHIMURA, Takashi, FUJINO, Shigehiro, KAWASAKI, Motoki, FUKATA, Syo
Format:	Patent
Sprache:	eng
Schlagworte:	BASIC ELECTRIC ELEMENTS ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ELECTRICITY SEMICONDUCTOR DEVICES
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