HYBRID DIFFUSION BREAK WITH EUV GATE PATTERNING
An apparatus comprising a substrate, a first nanosheet device located on the substrate, and a second nanosheet device located on the substrate, wherein the second nanosheet device is adjacent to the first nanosheet device. At least one first gate located on the first nanosheet device, wherein the at...
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creator | Miller, Eric Greene, Andrew M Seshadri, Indira Basker, Veeraraghavan S Frougier, Julien |
description | An apparatus comprising a substrate, a first nanosheet device located on the substrate, and a second nanosheet device located on the substrate, wherein the second nanosheet device is adjacent to the first nanosheet device. At least one first gate located on the first nanosheet device, wherein the at least one first gate has a first width. At least one second gate located on the second nanosheet device, wherein the at least one second gate has a second width, wherein the first width and the second width are substantially the same. A diffusion break located between the first nanosheet device and the second nanosheet device, wherein the diffusion break prevents the first nanosheet device from contacting the second nanosheet device, wherein the diffusion break has a third width, wherein the third width is larger than the first width and the second width. |
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At least one first gate located on the first nanosheet device, wherein the at least one first gate has a first width. At least one second gate located on the second nanosheet device, wherein the at least one second gate has a second width, wherein the first width and the second width are substantially the same. A diffusion break located between the first nanosheet device and the second nanosheet device, wherein the diffusion break prevents the first nanosheet device from contacting the second nanosheet device, wherein the diffusion break has a third width, wherein the third width is larger than the first width and the second width.</description><language>eng</language><subject>BASIC ELECTRIC ELEMENTS ; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ; ELECTRICITY ; SEMICONDUCTOR DEVICES</subject><creationdate>2022</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20221201&DB=EPODOC&CC=US&NR=2022384568A1$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,776,881,25542,76289</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20221201&DB=EPODOC&CC=US&NR=2022384568A1$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>Miller, Eric</creatorcontrib><creatorcontrib>Greene, Andrew M</creatorcontrib><creatorcontrib>Seshadri, Indira</creatorcontrib><creatorcontrib>Basker, Veeraraghavan S</creatorcontrib><creatorcontrib>Frougier, Julien</creatorcontrib><title>HYBRID DIFFUSION BREAK WITH EUV GATE PATTERNING</title><description>An apparatus comprising a substrate, a first nanosheet device located on the substrate, and a second nanosheet device located on the substrate, wherein the second nanosheet device is adjacent to the first nanosheet device. At least one first gate located on the first nanosheet device, wherein the at least one first gate has a first width. At least one second gate located on the second nanosheet device, wherein the at least one second gate has a second width, wherein the first width and the second width are substantially the same. A diffusion break located between the first nanosheet device and the second nanosheet device, wherein the diffusion break prevents the first nanosheet device from contacting the second nanosheet device, wherein the diffusion break has a third width, wherein the third width is larger than the first width and the second width.</description><subject>BASIC ELECTRIC ELEMENTS</subject><subject>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</subject><subject>ELECTRICITY</subject><subject>SEMICONDUCTOR DEVICES</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2022</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZND3iHQK8nRRcPF0cwsN9vT3U3AKcnX0Vgj3DPFQcA0NU3B3DHFVCHAMCXEN8vP0c-dhYE1LzClO5YXS3AzKbq4hzh66qQX58anFBYnJqXmpJfGhwUYGRkbGFiamZhaOhsbEqQIAmTUm8Q</recordid><startdate>20221201</startdate><enddate>20221201</enddate><creator>Miller, Eric</creator><creator>Greene, Andrew M</creator><creator>Seshadri, Indira</creator><creator>Basker, Veeraraghavan S</creator><creator>Frougier, Julien</creator><scope>EVB</scope></search><sort><creationdate>20221201</creationdate><title>HYBRID DIFFUSION BREAK WITH EUV GATE PATTERNING</title><author>Miller, Eric ; Greene, Andrew M ; Seshadri, Indira ; Basker, Veeraraghavan S ; Frougier, Julien</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_US2022384568A13</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>2022</creationdate><topic>BASIC ELECTRIC ELEMENTS</topic><topic>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</topic><topic>ELECTRICITY</topic><topic>SEMICONDUCTOR DEVICES</topic><toplevel>online_resources</toplevel><creatorcontrib>Miller, Eric</creatorcontrib><creatorcontrib>Greene, Andrew M</creatorcontrib><creatorcontrib>Seshadri, Indira</creatorcontrib><creatorcontrib>Basker, Veeraraghavan S</creatorcontrib><creatorcontrib>Frougier, Julien</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Miller, Eric</au><au>Greene, Andrew M</au><au>Seshadri, Indira</au><au>Basker, Veeraraghavan S</au><au>Frougier, Julien</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>HYBRID DIFFUSION BREAK WITH EUV GATE PATTERNING</title><date>2022-12-01</date><risdate>2022</risdate><abstract>An apparatus comprising a substrate, a first nanosheet device located on the substrate, and a second nanosheet device located on the substrate, wherein the second nanosheet device is adjacent to the first nanosheet device. At least one first gate located on the first nanosheet device, wherein the at least one first gate has a first width. At least one second gate located on the second nanosheet device, wherein the at least one second gate has a second width, wherein the first width and the second width are substantially the same. A diffusion break located between the first nanosheet device and the second nanosheet device, wherein the diffusion break prevents the first nanosheet device from contacting the second nanosheet device, wherein the diffusion break has a third width, wherein the third width is larger than the first width and the second width.</abstract><oa>free_for_read</oa></addata></record> |
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subjects | BASIC ELECTRIC ELEMENTS ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ELECTRICITY SEMICONDUCTOR DEVICES |
title | HYBRID DIFFUSION BREAK WITH EUV GATE PATTERNING |
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