THREE-DIMENSIONAL (3D) NAND COMPONENT WITH CONTROL CIRCUITRY ACROSS MULTIPLE WAFERS

THREE-DIMENSIONAL (3D) NAND COMPONENT WITH CONTROL CIRCUITRY ACROSS MULTIPLE WAFERS

Three-dimensional (3D) NAND components formed with control circuitry split across two wafers can provide for more area for control circuitry for an array, enabling improved 3D NAND system performance. In one example, a 3D NAND component includes a first die including a three-dimensional (3D) NAND ar...

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Hauptverfasser: JUNGROTH, Owen, HASNAT, Khaled, MAJHI, Prashant, FASTOW, Richard, PARAT, Krishna K
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BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
SEMICONDUCTOR DEVICES
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creator JUNGROTH, Owen
HASNAT, Khaled
MAJHI, Prashant
FASTOW, Richard
PARAT, Krishna K
description Three-dimensional (3D) NAND components formed with control circuitry split across two wafers can provide for more area for control circuitry for an array, enabling improved 3D NAND system performance. In one example, a 3D NAND component includes a first die including a three-dimensional (3D) NAND array and first complementary metal oxide semiconductor (CMOS) control circuitry to access the 3D NAND array, and a second die vertically stacked and bonded with the first die, the second die including second CMOS control circuitry to access the 3D NAND array of the first die.
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fullrecord <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_US2022359441A1</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>US2022359441A1</sourcerecordid><originalsourceid>FETCH-epo_espacenet_US2022359441A13</originalsourceid><addsrcrecordid>eNrjZAgO8QhyddV18fR19Qv29Pdz9FHQMHbRVPBz9HNRcPb3DfD3c_ULUQj3DPEAcv1Cgvx9FJw9g5xDPUOCIhUcnYP8g4MVfEN9QjwDfFwVwh3dXIOCeRhY0xJzilN5oTQ3g7Kba4izh25qQX58anFBYnJqXmpJfGiwkYGRkbGppYmJoaOhMXGqALikMNw</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>THREE-DIMENSIONAL (3D) NAND COMPONENT WITH CONTROL CIRCUITRY ACROSS MULTIPLE WAFERS</title><source>esp@cenet</source><creator>JUNGROTH, Owen ; HASNAT, Khaled ; MAJHI, Prashant ; FASTOW, Richard ; PARAT, Krishna K</creator><creatorcontrib>JUNGROTH, Owen ; HASNAT, Khaled ; MAJHI, Prashant ; FASTOW, Richard ; PARAT, Krishna K</creatorcontrib><description>Three-dimensional (3D) NAND components formed with control circuitry split across two wafers can provide for more area for control circuitry for an array, enabling improved 3D NAND system performance. In one example, a 3D NAND component includes a first die including a three-dimensional (3D) NAND array and first complementary metal oxide semiconductor (CMOS) control circuitry to access the 3D NAND array, and a second die vertically stacked and bonded with the first die, the second die including second CMOS control circuitry to access the 3D NAND array of the first die.</description><language>eng</language><subject>BASIC ELECTRIC ELEMENTS ; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ; ELECTRICITY ; SEMICONDUCTOR DEVICES</subject><creationdate>2022</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=20221110&amp;DB=EPODOC&amp;CC=US&amp;NR=2022359441A1$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,309,781,886,25569,76552</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=20221110&amp;DB=EPODOC&amp;CC=US&amp;NR=2022359441A1$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>JUNGROTH, Owen</creatorcontrib><creatorcontrib>HASNAT, Khaled</creatorcontrib><creatorcontrib>MAJHI, Prashant</creatorcontrib><creatorcontrib>FASTOW, Richard</creatorcontrib><creatorcontrib>PARAT, Krishna K</creatorcontrib><title>THREE-DIMENSIONAL (3D) NAND COMPONENT WITH CONTROL CIRCUITRY ACROSS MULTIPLE WAFERS</title><description>Three-dimensional (3D) NAND components formed with control circuitry split across two wafers can provide for more area for control circuitry for an array, enabling improved 3D NAND system performance. In one example, a 3D NAND component includes a first die including a three-dimensional (3D) NAND array and first complementary metal oxide semiconductor (CMOS) control circuitry to access the 3D NAND array, and a second die vertically stacked and bonded with the first die, the second die including second CMOS control circuitry to access the 3D NAND array of the first die.</description><subject>BASIC ELECTRIC ELEMENTS</subject><subject>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</subject><subject>ELECTRICITY</subject><subject>SEMICONDUCTOR DEVICES</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2022</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZAgO8QhyddV18fR19Qv29Pdz9FHQMHbRVPBz9HNRcPb3DfD3c_ULUQj3DPEAcv1Cgvx9FJw9g5xDPUOCIhUcnYP8g4MVfEN9QjwDfFwVwh3dXIOCeRhY0xJzilN5oTQ3g7Kba4izh25qQX58anFBYnJqXmpJfGiwkYGRkbGppYmJoaOhMXGqALikMNw</recordid><startdate>20221110</startdate><enddate>20221110</enddate><creator>JUNGROTH, Owen</creator><creator>HASNAT, Khaled</creator><creator>MAJHI, Prashant</creator><creator>FASTOW, Richard</creator><creator>PARAT, Krishna K</creator><scope>EVB</scope></search><sort><creationdate>20221110</creationdate><title>THREE-DIMENSIONAL (3D) NAND COMPONENT WITH CONTROL CIRCUITRY ACROSS MULTIPLE WAFERS</title><author>JUNGROTH, Owen ; HASNAT, Khaled ; MAJHI, Prashant ; FASTOW, Richard ; PARAT, Krishna K</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_US2022359441A13</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>2022</creationdate><topic>BASIC ELECTRIC ELEMENTS</topic><topic>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</topic><topic>ELECTRICITY</topic><topic>SEMICONDUCTOR DEVICES</topic><toplevel>online_resources</toplevel><creatorcontrib>JUNGROTH, Owen</creatorcontrib><creatorcontrib>HASNAT, Khaled</creatorcontrib><creatorcontrib>MAJHI, Prashant</creatorcontrib><creatorcontrib>FASTOW, Richard</creatorcontrib><creatorcontrib>PARAT, Krishna K</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>JUNGROTH, Owen</au><au>HASNAT, Khaled</au><au>MAJHI, Prashant</au><au>FASTOW, Richard</au><au>PARAT, Krishna K</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>THREE-DIMENSIONAL (3D) NAND COMPONENT WITH CONTROL CIRCUITRY ACROSS MULTIPLE WAFERS</title><date>2022-11-10</date><risdate>2022</risdate><abstract>Three-dimensional (3D) NAND components formed with control circuitry split across two wafers can provide for more area for control circuitry for an array, enabling improved 3D NAND system performance. In one example, a 3D NAND component includes a first die including a three-dimensional (3D) NAND array and first complementary metal oxide semiconductor (CMOS) control circuitry to access the 3D NAND array, and a second die vertically stacked and bonded with the first die, the second die including second CMOS control circuitry to access the 3D NAND array of the first die.</abstract><oa>free_for_read</oa></addata></record>
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subjects BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
SEMICONDUCTOR DEVICES
title THREE-DIMENSIONAL (3D) NAND COMPONENT WITH CONTROL CIRCUITRY ACROSS MULTIPLE WAFERS
url https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2024-12-15T16%3A40%3A24IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-epo_EVB&rft_val_fmt=info:ofi/fmt:kev:mtx:patent&rft.genre=patent&rft.au=JUNGROTH,%20Owen&rft.date=2022-11-10&rft_id=info:doi/&rft_dat=%3Cepo_EVB%3EUS2022359441A1%3C/epo_EVB%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rfr_iscdi=true