MEMORY CONTROLLER WITH STAGGERED REQUEST SIGNAL OUTPUT

A memory controller having a time-staggered request signal output. A first timing signal is generated while a second timing signal is generated having a first phase difference relative to the first timing signal. An address value is transmitted in response to the first timing signal and a control va...

Ausführliche Beschreibung

Gespeichert in:

Bibliographische Detailangaben
Hauptverfasser:	Stott, Bret, Lau, Benedict C, Shaeffer, Ian P
Format:	Patent
Sprache:	eng
Schlagworte:	CALCULATING COMPUTING COUNTING ELECTRIC DIGITAL DATA PROCESSING INFORMATION STORAGE PHYSICS STATIC STORES
Online-Zugang:	Volltext bestellen
Tags:	Tag hinzufügen Keine Tags, Fügen Sie den ersten Tag hinzu!

container_end_page
container_issue
container_start_page
container_title
container_volume
creator	Stott, Bret Lau, Benedict C Shaeffer, Ian P
description	A memory controller having a time-staggered request signal output. A first timing signal is generated while a second timing signal is generated having a first phase difference relative to the first timing signal. An address value is transmitted in response to the first timing signal and a control value is transmitted in response to the second timing signal, the address value and control value constituting portions of a first memory access request.
format	Patent
fullrecord	<record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_US2022343956A1</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>US2022343956A1</sourcerecordid><originalsourceid>FETCH-epo_espacenet_US2022343956A13</originalsourceid><addsrcrecordid>eNrjZDDzdfX1D4pUcPb3Cwny9_FxDVII9wzxUAgOcXR3dw1ydVEIcg0MdQ0OUQj2dPdz9FHwDw0JCA3hYWBNS8wpTuWF0twMym6uIc4euqkF-fGpxQWJyal5qSXxocFGBkZGxibGlqZmjobGxKkCAO8gKWA</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>MEMORY CONTROLLER WITH STAGGERED REQUEST SIGNAL OUTPUT</title><source>esp@cenet</source><creator>Stott, Bret ; Lau, Benedict C ; Shaeffer, Ian P</creator><creatorcontrib>Stott, Bret ; Lau, Benedict C ; Shaeffer, Ian P</creatorcontrib><description>A memory controller having a time-staggered request signal output. A first timing signal is generated while a second timing signal is generated having a first phase difference relative to the first timing signal. An address value is transmitted in response to the first timing signal and a control value is transmitted in response to the second timing signal, the address value and control value constituting portions of a first memory access request.</description><language>eng</language><subject>CALCULATING ; COMPUTING ; COUNTING ; ELECTRIC DIGITAL DATA PROCESSING ; INFORMATION STORAGE ; PHYSICS ; STATIC STORES</subject><creationdate>2022</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20221027&DB=EPODOC&CC=US&NR=2022343956A1$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,780,885,25563,76318</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20221027&DB=EPODOC&CC=US&NR=2022343956A1$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>Stott, Bret</creatorcontrib><creatorcontrib>Lau, Benedict C</creatorcontrib><creatorcontrib>Shaeffer, Ian P</creatorcontrib><title>MEMORY CONTROLLER WITH STAGGERED REQUEST SIGNAL OUTPUT</title><description>A memory controller having a time-staggered request signal output. A first timing signal is generated while a second timing signal is generated having a first phase difference relative to the first timing signal. An address value is transmitted in response to the first timing signal and a control value is transmitted in response to the second timing signal, the address value and control value constituting portions of a first memory access request.</description><subject>CALCULATING</subject><subject>COMPUTING</subject><subject>COUNTING</subject><subject>ELECTRIC DIGITAL DATA PROCESSING</subject><subject>INFORMATION STORAGE</subject><subject>PHYSICS</subject><subject>STATIC STORES</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2022</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZDDzdfX1D4pUcPb3Cwny9_FxDVII9wzxUAgOcXR3dw1ydVEIcg0MdQ0OUQj2dPdz9FHwDw0JCA3hYWBNS8wpTuWF0twMym6uIc4euqkF-fGpxQWJyal5qSXxocFGBkZGxibGlqZmjobGxKkCAO8gKWA</recordid><startdate>20221027</startdate><enddate>20221027</enddate><creator>Stott, Bret</creator><creator>Lau, Benedict C</creator><creator>Shaeffer, Ian P</creator><scope>EVB</scope></search><sort><creationdate>20221027</creationdate><title>MEMORY CONTROLLER WITH STAGGERED REQUEST SIGNAL OUTPUT</title><author>Stott, Bret ; Lau, Benedict C ; Shaeffer, Ian P</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_US2022343956A13</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>2022</creationdate><topic>CALCULATING</topic><topic>COMPUTING</topic><topic>COUNTING</topic><topic>ELECTRIC DIGITAL DATA PROCESSING</topic><topic>INFORMATION STORAGE</topic><topic>PHYSICS</topic><topic>STATIC STORES</topic><toplevel>online_resources</toplevel><creatorcontrib>Stott, Bret</creatorcontrib><creatorcontrib>Lau, Benedict C</creatorcontrib><creatorcontrib>Shaeffer, Ian P</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Stott, Bret</au><au>Lau, Benedict C</au><au>Shaeffer, Ian P</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>MEMORY CONTROLLER WITH STAGGERED REQUEST SIGNAL OUTPUT</title><date>2022-10-27</date><risdate>2022</risdate><abstract>A memory controller having a time-staggered request signal output. A first timing signal is generated while a second timing signal is generated having a first phase difference relative to the first timing signal. An address value is transmitted in response to the first timing signal and a control value is transmitted in response to the second timing signal, the address value and control value constituting portions of a first memory access request.</abstract><oa>free_for_read</oa></addata></record>
fulltext	fulltext_linktorsrc
identifier
ispartof
issn
language	eng
recordid	cdi_epo_espacenet_US2022343956A1
source	esp@cenet
subjects	CALCULATING COMPUTING COUNTING ELECTRIC DIGITAL DATA PROCESSING INFORMATION STORAGE PHYSICS STATIC STORES
title	MEMORY CONTROLLER WITH STAGGERED REQUEST SIGNAL OUTPUT
url	https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-01-13T01%3A15%3A17IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-epo_EVB&rft_val_fmt=info:ofi/fmt:kev:mtx:patent&rft.genre=patent&rft.au=Stott,%20Bret&rft.date=2022-10-27&rft_id=info:doi/&rft_dat=%3Cepo_EVB%3EUS2022343956A1%3C/epo_EVB%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rfr_iscdi=true