GENERATING A REDUCED BLOCK MODEL VIEW ON-THE-FLY

GENERATING A REDUCED BLOCK MODEL VIEW ON-THE-FLY

A word-level design model may be loaded into memory. Next, a masking layer may be created which includes objects in the word-level design model that are not used by an IC design analysis system. The masking layer may then be used to provide a reduced block model view on-the-fly to the IC design anal...

Ausführliche Beschreibung

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Bibliographische Detailangaben
Hauptverfasser: Narwade, Mahantesh D, Singla, Abhinav, Varkey, Vijaya V, Ghosh, Soumen, Mukherjee, Rajarshi, Roizman, Mark
Format: Patent
Sprache:eng
Schlagworte:
CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
PHYSICS
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Beschreibung
Zusammenfassung:A word-level design model may be loaded into memory. Next, a masking layer may be created which includes objects in the word-level design model that are not used by an IC design analysis system. The masking layer may then be used to provide a reduced block model view on-the-fly to the IC design analysis system.