SYSTEMS AND METHODS FOR AN INTELLIGENT MAPPING OF NEURAL NETWORK WEIGHTS AND INPUT DATA TO AN ARRAY OF PROCESSING CORES OF AN INTEGRATED CIRCUIT

Systems and methods of configuring an array of processors of an integrated circuit includes identifying a fast Fourier transform (FFT) matrix multiply of input data, wherein the FFT matrix multiply of the input data includes a bit-reversed input array, configuring the array of processing cores based...

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Hauptverfasser: Kheterpal, Veerbhan, Drego, Nigel, Sikka, Aman, Firu, Daniel
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creator Kheterpal, Veerbhan
Drego, Nigel
Sikka, Aman
Firu, Daniel
description Systems and methods of configuring an array of processors of an integrated circuit includes identifying a fast Fourier transform (FFT) matrix multiply of input data, wherein the FFT matrix multiply of the input data includes a bit-reversed input array, configuring the array of processing cores based on the bit-reversed input array, wherein the configuring the array of processing cores includes storing the input bits of the bit-reversed input array within memory circuits of distinct processing cores of an array of processing cores of the integrated circuit based on an input bit mapping that identifies a pre-determined storage location within the array of processing cores of each input bit of the bit-reversed input array, and performing matrix multiply computations between weight stages of the FFT matrix multiply and the input bits of the bit-reversed input array stored within the memory circuits of the distinct processing cores.
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fullrecord <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_US2022284074A1</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>US2022284074A1</sourcerecordid><originalsourceid>FETCH-epo_espacenet_US2022284074A13</originalsourceid><addsrcrecordid>eNqNjUELgkAUhL10iOo_POgcmAl1faxPXdJdeftEPInEdooS7If0k1PyB3QaZpj5Zh18XOuESgdoEihJcps4SC1PHrQRKgqdkREosaq0ycCmYKhmLCaRxvIVGtJZLj-ANlUtkKAgiJ0RyIztPKrYKnJuRijL5OZsucgYhRJQmlWtZRus7v1j9LtFN8E-JVH5wQ-vzo9Df_NP_-5qF4VRFF3i8Bzj8fRf6wsmnUEk</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>SYSTEMS AND METHODS FOR AN INTELLIGENT MAPPING OF NEURAL NETWORK WEIGHTS AND INPUT DATA TO AN ARRAY OF PROCESSING CORES OF AN INTEGRATED CIRCUIT</title><source>esp@cenet</source><creator>Kheterpal, Veerbhan ; Drego, Nigel ; Sikka, Aman ; Firu, Daniel</creator><creatorcontrib>Kheterpal, Veerbhan ; Drego, Nigel ; Sikka, Aman ; Firu, Daniel</creatorcontrib><description>Systems and methods of configuring an array of processors of an integrated circuit includes identifying a fast Fourier transform (FFT) matrix multiply of input data, wherein the FFT matrix multiply of the input data includes a bit-reversed input array, configuring the array of processing cores based on the bit-reversed input array, wherein the configuring the array of processing cores includes storing the input bits of the bit-reversed input array within memory circuits of distinct processing cores of an array of processing cores of the integrated circuit based on an input bit mapping that identifies a pre-determined storage location within the array of processing cores of each input bit of the bit-reversed input array, and performing matrix multiply computations between weight stages of the FFT matrix multiply and the input bits of the bit-reversed input array stored within the memory circuits of the distinct processing cores.</description><language>eng</language><subject>CALCULATING ; COMPUTING ; COUNTING ; ELECTRIC DIGITAL DATA PROCESSING ; PHYSICS</subject><creationdate>2022</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=20220908&amp;DB=EPODOC&amp;CC=US&amp;NR=2022284074A1$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,776,881,25542,76516</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=20220908&amp;DB=EPODOC&amp;CC=US&amp;NR=2022284074A1$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>Kheterpal, Veerbhan</creatorcontrib><creatorcontrib>Drego, Nigel</creatorcontrib><creatorcontrib>Sikka, Aman</creatorcontrib><creatorcontrib>Firu, Daniel</creatorcontrib><title>SYSTEMS AND METHODS FOR AN INTELLIGENT MAPPING OF NEURAL NETWORK WEIGHTS AND INPUT DATA TO AN ARRAY OF PROCESSING CORES OF AN INTEGRATED CIRCUIT</title><description>Systems and methods of configuring an array of processors of an integrated circuit includes identifying a fast Fourier transform (FFT) matrix multiply of input data, wherein the FFT matrix multiply of the input data includes a bit-reversed input array, configuring the array of processing cores based on the bit-reversed input array, wherein the configuring the array of processing cores includes storing the input bits of the bit-reversed input array within memory circuits of distinct processing cores of an array of processing cores of the integrated circuit based on an input bit mapping that identifies a pre-determined storage location within the array of processing cores of each input bit of the bit-reversed input array, and performing matrix multiply computations between weight stages of the FFT matrix multiply and the input bits of the bit-reversed input array stored within the memory circuits of the distinct processing cores.</description><subject>CALCULATING</subject><subject>COMPUTING</subject><subject>COUNTING</subject><subject>ELECTRIC DIGITAL DATA PROCESSING</subject><subject>PHYSICS</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2022</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNqNjUELgkAUhL10iOo_POgcmAl1faxPXdJdeftEPInEdooS7If0k1PyB3QaZpj5Zh18XOuESgdoEihJcps4SC1PHrQRKgqdkREosaq0ycCmYKhmLCaRxvIVGtJZLj-ANlUtkKAgiJ0RyIztPKrYKnJuRijL5OZsucgYhRJQmlWtZRus7v1j9LtFN8E-JVH5wQ-vzo9Df_NP_-5qF4VRFF3i8Bzj8fRf6wsmnUEk</recordid><startdate>20220908</startdate><enddate>20220908</enddate><creator>Kheterpal, Veerbhan</creator><creator>Drego, Nigel</creator><creator>Sikka, Aman</creator><creator>Firu, Daniel</creator><scope>EVB</scope></search><sort><creationdate>20220908</creationdate><title>SYSTEMS AND METHODS FOR AN INTELLIGENT MAPPING OF NEURAL NETWORK WEIGHTS AND INPUT DATA TO AN ARRAY OF PROCESSING CORES OF AN INTEGRATED CIRCUIT</title><author>Kheterpal, Veerbhan ; Drego, Nigel ; Sikka, Aman ; Firu, Daniel</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_US2022284074A13</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>2022</creationdate><topic>CALCULATING</topic><topic>COMPUTING</topic><topic>COUNTING</topic><topic>ELECTRIC DIGITAL DATA PROCESSING</topic><topic>PHYSICS</topic><toplevel>online_resources</toplevel><creatorcontrib>Kheterpal, Veerbhan</creatorcontrib><creatorcontrib>Drego, Nigel</creatorcontrib><creatorcontrib>Sikka, Aman</creatorcontrib><creatorcontrib>Firu, Daniel</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Kheterpal, Veerbhan</au><au>Drego, Nigel</au><au>Sikka, Aman</au><au>Firu, Daniel</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>SYSTEMS AND METHODS FOR AN INTELLIGENT MAPPING OF NEURAL NETWORK WEIGHTS AND INPUT DATA TO AN ARRAY OF PROCESSING CORES OF AN INTEGRATED CIRCUIT</title><date>2022-09-08</date><risdate>2022</risdate><abstract>Systems and methods of configuring an array of processors of an integrated circuit includes identifying a fast Fourier transform (FFT) matrix multiply of input data, wherein the FFT matrix multiply of the input data includes a bit-reversed input array, configuring the array of processing cores based on the bit-reversed input array, wherein the configuring the array of processing cores includes storing the input bits of the bit-reversed input array within memory circuits of distinct processing cores of an array of processing cores of the integrated circuit based on an input bit mapping that identifies a pre-determined storage location within the array of processing cores of each input bit of the bit-reversed input array, and performing matrix multiply computations between weight stages of the FFT matrix multiply and the input bits of the bit-reversed input array stored within the memory circuits of the distinct processing cores.</abstract><oa>free_for_read</oa></addata></record>
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subjects CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
PHYSICS
title SYSTEMS AND METHODS FOR AN INTELLIGENT MAPPING OF NEURAL NETWORK WEIGHTS AND INPUT DATA TO AN ARRAY OF PROCESSING CORES OF AN INTEGRATED CIRCUIT
url https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-02-15T14%3A59%3A07IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-epo_EVB&rft_val_fmt=info:ofi/fmt:kev:mtx:patent&rft.genre=patent&rft.au=Kheterpal,%20Veerbhan&rft.date=2022-09-08&rft_id=info:doi/&rft_dat=%3Cepo_EVB%3EUS2022284074A1%3C/epo_EVB%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rfr_iscdi=true