ACCELERATOR CONTROL SYSTEM AND ACCELERATOR CONTROL METHOD
In an accelerator control system (100), a general-purpose server (110) includes a digest information generation unit (1112) that binarizes an accelerator function to generate first digest information (130) of the accelerator function and a server management control unit (1111) that compares the firs...
Gespeichert in:
| Hauptverfasser: | , |
|---|---|
| Format: | Patent |
| Sprache: | eng |
| Schlagworte: | |
| Online-Zugang: | Volltext bestellen |
| Tags: |
Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
|
| container_end_page | |
|---|---|
| container_issue | |
| container_start_page | |
| container_title | |
| container_volume | |
| creator | OTANI, Ikuo HORIKOME, Noritaka |
| description | In an accelerator control system (100), a general-purpose server (110) includes a digest information generation unit (1112) that binarizes an accelerator function to generate first digest information (130) of the accelerator function and a server management control unit (1111) that compares the first digest information (130) created before the accelerator function is implemented on an FPGA function unit (122) with second digest information (130) notified from an accelerator board (120) and determines whether the accelerator function is rewritten, and the accelerator board (120) includes a digest information generation unit (1212) that generates the second digest information (130) of the accelerator function written in the FPGA function unit (122), and an FPGA management control unit (1211) that notifies the general-purpose server (110) serving as a rewriting source of the second digest information (130) generated. |
| format | Patent |
| fullrecord | <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_US2022283868A1</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>US2022283868A1</sourcerecordid><originalsourceid>FETCH-epo_espacenet_US2022283868A13</originalsourceid><addsrcrecordid>eNrjZLB0dHZ29XENcgzxD1Jw9vcLCfL3UQiODA5x9VVw9HNRwCbt6xri4e_Cw8CalphTnMoLpbkZlN1cQ5w9dFML8uNTiwsSk1PzUkviQ4ONDIyMjCyMLcwsHA2NiVMFAEUEKes</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>ACCELERATOR CONTROL SYSTEM AND ACCELERATOR CONTROL METHOD</title><source>esp@cenet</source><creator>OTANI, Ikuo ; HORIKOME, Noritaka</creator><creatorcontrib>OTANI, Ikuo ; HORIKOME, Noritaka</creatorcontrib><description>In an accelerator control system (100), a general-purpose server (110) includes a digest information generation unit (1112) that binarizes an accelerator function to generate first digest information (130) of the accelerator function and a server management control unit (1111) that compares the first digest information (130) created before the accelerator function is implemented on an FPGA function unit (122) with second digest information (130) notified from an accelerator board (120) and determines whether the accelerator function is rewritten, and the accelerator board (120) includes a digest information generation unit (1212) that generates the second digest information (130) of the accelerator function written in the FPGA function unit (122), and an FPGA management control unit (1211) that notifies the general-purpose server (110) serving as a rewriting source of the second digest information (130) generated.</description><language>eng</language><subject>CALCULATING ; COMPUTING ; COUNTING ; ELECTRIC DIGITAL DATA PROCESSING ; PHYSICS</subject><creationdate>2022</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20220908&DB=EPODOC&CC=US&NR=2022283868A1$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,309,781,886,25569,76552</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20220908&DB=EPODOC&CC=US&NR=2022283868A1$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>OTANI, Ikuo</creatorcontrib><creatorcontrib>HORIKOME, Noritaka</creatorcontrib><title>ACCELERATOR CONTROL SYSTEM AND ACCELERATOR CONTROL METHOD</title><description>In an accelerator control system (100), a general-purpose server (110) includes a digest information generation unit (1112) that binarizes an accelerator function to generate first digest information (130) of the accelerator function and a server management control unit (1111) that compares the first digest information (130) created before the accelerator function is implemented on an FPGA function unit (122) with second digest information (130) notified from an accelerator board (120) and determines whether the accelerator function is rewritten, and the accelerator board (120) includes a digest information generation unit (1212) that generates the second digest information (130) of the accelerator function written in the FPGA function unit (122), and an FPGA management control unit (1211) that notifies the general-purpose server (110) serving as a rewriting source of the second digest information (130) generated.</description><subject>CALCULATING</subject><subject>COMPUTING</subject><subject>COUNTING</subject><subject>ELECTRIC DIGITAL DATA PROCESSING</subject><subject>PHYSICS</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2022</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZLB0dHZ29XENcgzxD1Jw9vcLCfL3UQiODA5x9VVw9HNRwCbt6xri4e_Cw8CalphTnMoLpbkZlN1cQ5w9dFML8uNTiwsSk1PzUkviQ4ONDIyMjCyMLcwsHA2NiVMFAEUEKes</recordid><startdate>20220908</startdate><enddate>20220908</enddate><creator>OTANI, Ikuo</creator><creator>HORIKOME, Noritaka</creator><scope>EVB</scope></search><sort><creationdate>20220908</creationdate><title>ACCELERATOR CONTROL SYSTEM AND ACCELERATOR CONTROL METHOD</title><author>OTANI, Ikuo ; HORIKOME, Noritaka</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_US2022283868A13</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>2022</creationdate><topic>CALCULATING</topic><topic>COMPUTING</topic><topic>COUNTING</topic><topic>ELECTRIC DIGITAL DATA PROCESSING</topic><topic>PHYSICS</topic><toplevel>online_resources</toplevel><creatorcontrib>OTANI, Ikuo</creatorcontrib><creatorcontrib>HORIKOME, Noritaka</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>OTANI, Ikuo</au><au>HORIKOME, Noritaka</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>ACCELERATOR CONTROL SYSTEM AND ACCELERATOR CONTROL METHOD</title><date>2022-09-08</date><risdate>2022</risdate><abstract>In an accelerator control system (100), a general-purpose server (110) includes a digest information generation unit (1112) that binarizes an accelerator function to generate first digest information (130) of the accelerator function and a server management control unit (1111) that compares the first digest information (130) created before the accelerator function is implemented on an FPGA function unit (122) with second digest information (130) notified from an accelerator board (120) and determines whether the accelerator function is rewritten, and the accelerator board (120) includes a digest information generation unit (1212) that generates the second digest information (130) of the accelerator function written in the FPGA function unit (122), and an FPGA management control unit (1211) that notifies the general-purpose server (110) serving as a rewriting source of the second digest information (130) generated.</abstract><oa>free_for_read</oa></addata></record> |
| fulltext | fulltext_linktorsrc |
| identifier | |
| ispartof | |
| issn | |
| language | eng |
| recordid | cdi_epo_espacenet_US2022283868A1 |
| source | esp@cenet |
| subjects | CALCULATING COMPUTING COUNTING ELECTRIC DIGITAL DATA PROCESSING PHYSICS |
| title | ACCELERATOR CONTROL SYSTEM AND ACCELERATOR CONTROL METHOD |
| url | https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2024-12-15T19%3A38%3A27IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-epo_EVB&rft_val_fmt=info:ofi/fmt:kev:mtx:patent&rft.genre=patent&rft.au=OTANI,%20Ikuo&rft.date=2022-09-08&rft_id=info:doi/&rft_dat=%3Cepo_EVB%3EUS2022283868A1%3C/epo_EVB%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rfr_iscdi=true |