DMOS FET CHIP SCALE PACKAGE AND METHOD OF MAKING THE SAME

DMOS FET CHIP SCALE PACKAGE AND METHOD OF MAKING THE SAME

A method comprises the steps of providing a wafer; applying a redistribution layer, grinding a back side of the wafer; depositing a metal layer; and applying a singulation process. A semiconductor package comprises a metal-oxide-semiconductor field-effect transistor (MOSFET), a redistribution layer,...

Ausführliche Beschreibung

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Bibliographische Detailangaben
Hauptverfasser: Wang, Long-Ching, Bobde, Madhur, Xue, Yan Xun, Xue, Hongyong, Lu, Jun, Niu, Zhiqiang
Format: Patent
Sprache:eng
Schlagworte:
BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
SEMICONDUCTOR DEVICES
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Beschreibung
Zusammenfassung:A method comprises the steps of providing a wafer; applying a redistribution layer, grinding a back side of the wafer; depositing a metal layer; and applying a singulation process. A semiconductor package comprises a metal-oxide-semiconductor field-effect transistor (MOSFET), a redistribution layer, and a metal layer. The MOSFET comprises a source electrode, a gate electrode, a drain electrode and a plurality of partial drain plugs. The source electrode, the gate electrode, and the drain electrode are positioned at a front side of the MOSFET.