REDUCTION AND ACCELERATION OF A DETERMINISTIC FINITE AUTOMATON

REDUCTION AND ACCELERATION OF A DETERMINISTIC FINITE AUTOMATON

Techniques for reduction and acceleration of a deterministic finite automaton (DFA) are disclosed. In some embodiments, a system, process, and/or computer program product for reduction and acceleration of a DFA includes receiving an input value; performing a reduced deterministic finite automaton lo...

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Hauptverfasser: Ganesh, Subramani, Chang, Lei, Li, Sidong
Format: Patent
Sprache:eng
Schlagworte:
CALCULATING
COMPUTING
COUNTING
ELECTRIC COMMUNICATION TECHNIQUE
ELECTRIC DIGITAL DATA PROCESSING
ELECTRICITY
PHYSICS
TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHICCOMMUNICATION
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creator Ganesh, Subramani
Chang, Lei
Li, Sidong
description Techniques for reduction and acceleration of a deterministic finite automaton (DFA) are disclosed. In some embodiments, a system, process, and/or computer program product for reduction and acceleration of a DFA includes receiving an input value; performing a reduced deterministic finite automaton lookup using a lookup key, wherein the lookup key comprises a current state and the input value; and determining a next state based on the lookup key.
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fullrecord <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_US2022272072A1</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>US2022272072A1</sourcerecordid><originalsourceid>FETCH-epo_espacenet_US2022272072A13</originalsourceid><addsrcrecordid>eNrjZLALcnUJdQ7x9PdTcPRzUXB0dnb1cQ1yBAv4uyk4Kri4hrgG-Xr6eQaHeDoruAEZIa4KjqEh_r6OIf5-PAysaYk5xam8UJqbQdnNNcTZQze1ID8-tbggMTk1L7UkPjTYyMDIyMjcyMDcyNHQmDhVAPZ3Kvg</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>REDUCTION AND ACCELERATION OF A DETERMINISTIC FINITE AUTOMATON</title><source>esp@cenet</source><creator>Ganesh, Subramani ; Chang, Lei ; Li, Sidong</creator><creatorcontrib>Ganesh, Subramani ; Chang, Lei ; Li, Sidong</creatorcontrib><description>Techniques for reduction and acceleration of a deterministic finite automaton (DFA) are disclosed. In some embodiments, a system, process, and/or computer program product for reduction and acceleration of a DFA includes receiving an input value; performing a reduced deterministic finite automaton lookup using a lookup key, wherein the lookup key comprises a current state and the input value; and determining a next state based on the lookup key.</description><language>eng</language><subject>CALCULATING ; COMPUTING ; COUNTING ; ELECTRIC COMMUNICATION TECHNIQUE ; ELECTRIC DIGITAL DATA PROCESSING ; ELECTRICITY ; PHYSICS ; TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHICCOMMUNICATION</subject><creationdate>2022</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=20220825&amp;DB=EPODOC&amp;CC=US&amp;NR=2022272072A1$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,780,885,25564,76419</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=20220825&amp;DB=EPODOC&amp;CC=US&amp;NR=2022272072A1$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>Ganesh, Subramani</creatorcontrib><creatorcontrib>Chang, Lei</creatorcontrib><creatorcontrib>Li, Sidong</creatorcontrib><title>REDUCTION AND ACCELERATION OF A DETERMINISTIC FINITE AUTOMATON</title><description>Techniques for reduction and acceleration of a deterministic finite automaton (DFA) are disclosed. In some embodiments, a system, process, and/or computer program product for reduction and acceleration of a DFA includes receiving an input value; performing a reduced deterministic finite automaton lookup using a lookup key, wherein the lookup key comprises a current state and the input value; and determining a next state based on the lookup key.</description><subject>CALCULATING</subject><subject>COMPUTING</subject><subject>COUNTING</subject><subject>ELECTRIC COMMUNICATION TECHNIQUE</subject><subject>ELECTRIC DIGITAL DATA PROCESSING</subject><subject>ELECTRICITY</subject><subject>PHYSICS</subject><subject>TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHICCOMMUNICATION</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2022</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZLALcnUJdQ7x9PdTcPRzUXB0dnb1cQ1yBAv4uyk4Kri4hrgG-Xr6eQaHeDoruAEZIa4KjqEh_r6OIf5-PAysaYk5xam8UJqbQdnNNcTZQze1ID8-tbggMTk1L7UkPjTYyMDIyMjcyMDcyNHQmDhVAPZ3Kvg</recordid><startdate>20220825</startdate><enddate>20220825</enddate><creator>Ganesh, Subramani</creator><creator>Chang, Lei</creator><creator>Li, Sidong</creator><scope>EVB</scope></search><sort><creationdate>20220825</creationdate><title>REDUCTION AND ACCELERATION OF A DETERMINISTIC FINITE AUTOMATON</title><author>Ganesh, Subramani ; Chang, Lei ; Li, Sidong</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_US2022272072A13</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>2022</creationdate><topic>CALCULATING</topic><topic>COMPUTING</topic><topic>COUNTING</topic><topic>ELECTRIC COMMUNICATION TECHNIQUE</topic><topic>ELECTRIC DIGITAL DATA PROCESSING</topic><topic>ELECTRICITY</topic><topic>PHYSICS</topic><topic>TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHICCOMMUNICATION</topic><toplevel>online_resources</toplevel><creatorcontrib>Ganesh, Subramani</creatorcontrib><creatorcontrib>Chang, Lei</creatorcontrib><creatorcontrib>Li, Sidong</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Ganesh, Subramani</au><au>Chang, Lei</au><au>Li, Sidong</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>REDUCTION AND ACCELERATION OF A DETERMINISTIC FINITE AUTOMATON</title><date>2022-08-25</date><risdate>2022</risdate><abstract>Techniques for reduction and acceleration of a deterministic finite automaton (DFA) are disclosed. In some embodiments, a system, process, and/or computer program product for reduction and acceleration of a DFA includes receiving an input value; performing a reduced deterministic finite automaton lookup using a lookup key, wherein the lookup key comprises a current state and the input value; and determining a next state based on the lookup key.</abstract><oa>free_for_read</oa></addata></record>
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subjects CALCULATING
COMPUTING
COUNTING
ELECTRIC COMMUNICATION TECHNIQUE
ELECTRIC DIGITAL DATA PROCESSING
ELECTRICITY
PHYSICS
TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHICCOMMUNICATION
title REDUCTION AND ACCELERATION OF A DETERMINISTIC FINITE AUTOMATON
url https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-01-07T21%3A14%3A27IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-epo_EVB&rft_val_fmt=info:ofi/fmt:kev:mtx:patent&rft.genre=patent&rft.au=Ganesh,%20Subramani&rft.date=2022-08-25&rft_id=info:doi/&rft_dat=%3Cepo_EVB%3EUS2022272072A1%3C/epo_EVB%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rfr_iscdi=true