WIREBONDABLE INTERPOSER FOR FLIP CHIP PACKAGED INTEGRATED CIRCUIT DIE

WIREBONDABLE INTERPOSER FOR FLIP CHIP PACKAGED INTEGRATED CIRCUIT DIE

A variety of methods and arrangements to convert a flip chip IC die package into a wirebondable component using an interposer are described. The interposer has an insulating layer and a patterned metal layer attached to one side of the insulating layer. The patterned metal layer is electrically conn...

Ausführliche Beschreibung

Gespeichert in:
Bibliographische Detailangaben
Hauptverfasser: CHEN, Chihhao, LOY, Edwin, ZHAO, Yan Yang
Format: Patent
Sprache:eng
Schlagworte:
BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
SEMICONDUCTOR DEVICES
Online-Zugang:Volltext bestellen
Tags: Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
container_end_page
container_issue
container_start_page
container_title
container_volume
creator CHEN, Chihhao
LOY, Edwin
ZHAO, Yan Yang
description A variety of methods and arrangements to convert a flip chip IC die package into a wirebondable component using an interposer are described. The interposer has an insulating layer and a patterned metal layer attached to one side of the insulating layer. The patterned metal layer is electrically connected to the IC die using solder bumps. The interposer has wirebond pads on a side of the interposer opposed to the side of the interposer having the electrical connection between the IC die and solder bumps. The interposer may be a thin organic laminate or a flexible printed circuit board.
format Patent
fullrecord <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_US2022254707A1</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>US2022254707A1</sourcerecordid><originalsourceid>FETCH-epo_espacenet_US2022254707A13</originalsourceid><addsrcrecordid>eNrjZHAN9wxydfL3c3F08nFV8PQLcQ0K8A92DVJw8wdiH88ABWcPIBHg6Ozt6O7qAlbhHuQYAmQ6ewY5h3qGKLh4uvIwsKYl5hSn8kJpbgZlN9cQZw_d1IL8-NTigsTk1LzUkvjQYCMDIyMjUxNzA3NHQ2PiVAEAJLIsyQ</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>WIREBONDABLE INTERPOSER FOR FLIP CHIP PACKAGED INTEGRATED CIRCUIT DIE</title><source>esp@cenet</source><creator>CHEN, Chihhao ; LOY, Edwin ; ZHAO, Yan Yang</creator><creatorcontrib>CHEN, Chihhao ; LOY, Edwin ; ZHAO, Yan Yang</creatorcontrib><description>A variety of methods and arrangements to convert a flip chip IC die package into a wirebondable component using an interposer are described. The interposer has an insulating layer and a patterned metal layer attached to one side of the insulating layer. The patterned metal layer is electrically connected to the IC die using solder bumps. The interposer has wirebond pads on a side of the interposer opposed to the side of the interposer having the electrical connection between the IC die and solder bumps. The interposer may be a thin organic laminate or a flexible printed circuit board.</description><language>eng</language><subject>BASIC ELECTRIC ELEMENTS ; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ; ELECTRICITY ; SEMICONDUCTOR DEVICES</subject><creationdate>2022</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=20220811&amp;DB=EPODOC&amp;CC=US&amp;NR=2022254707A1$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,777,882,25546,76297</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=20220811&amp;DB=EPODOC&amp;CC=US&amp;NR=2022254707A1$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>CHEN, Chihhao</creatorcontrib><creatorcontrib>LOY, Edwin</creatorcontrib><creatorcontrib>ZHAO, Yan Yang</creatorcontrib><title>WIREBONDABLE INTERPOSER FOR FLIP CHIP PACKAGED INTEGRATED CIRCUIT DIE</title><description>A variety of methods and arrangements to convert a flip chip IC die package into a wirebondable component using an interposer are described. The interposer has an insulating layer and a patterned metal layer attached to one side of the insulating layer. The patterned metal layer is electrically connected to the IC die using solder bumps. The interposer has wirebond pads on a side of the interposer opposed to the side of the interposer having the electrical connection between the IC die and solder bumps. The interposer may be a thin organic laminate or a flexible printed circuit board.</description><subject>BASIC ELECTRIC ELEMENTS</subject><subject>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</subject><subject>ELECTRICITY</subject><subject>SEMICONDUCTOR DEVICES</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2022</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZHAN9wxydfL3c3F08nFV8PQLcQ0K8A92DVJw8wdiH88ABWcPIBHg6Ozt6O7qAlbhHuQYAmQ6ewY5h3qGKLh4uvIwsKYl5hSn8kJpbgZlN9cQZw_d1IL8-NTigsTk1LzUkvjQYCMDIyMjUxNzA3NHQ2PiVAEAJLIsyQ</recordid><startdate>20220811</startdate><enddate>20220811</enddate><creator>CHEN, Chihhao</creator><creator>LOY, Edwin</creator><creator>ZHAO, Yan Yang</creator><scope>EVB</scope></search><sort><creationdate>20220811</creationdate><title>WIREBONDABLE INTERPOSER FOR FLIP CHIP PACKAGED INTEGRATED CIRCUIT DIE</title><author>CHEN, Chihhao ; LOY, Edwin ; ZHAO, Yan Yang</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_US2022254707A13</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>2022</creationdate><topic>BASIC ELECTRIC ELEMENTS</topic><topic>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</topic><topic>ELECTRICITY</topic><topic>SEMICONDUCTOR DEVICES</topic><toplevel>online_resources</toplevel><creatorcontrib>CHEN, Chihhao</creatorcontrib><creatorcontrib>LOY, Edwin</creatorcontrib><creatorcontrib>ZHAO, Yan Yang</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>CHEN, Chihhao</au><au>LOY, Edwin</au><au>ZHAO, Yan Yang</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>WIREBONDABLE INTERPOSER FOR FLIP CHIP PACKAGED INTEGRATED CIRCUIT DIE</title><date>2022-08-11</date><risdate>2022</risdate><abstract>A variety of methods and arrangements to convert a flip chip IC die package into a wirebondable component using an interposer are described. The interposer has an insulating layer and a patterned metal layer attached to one side of the insulating layer. The patterned metal layer is electrically connected to the IC die using solder bumps. The interposer has wirebond pads on a side of the interposer opposed to the side of the interposer having the electrical connection between the IC die and solder bumps. The interposer may be a thin organic laminate or a flexible printed circuit board.</abstract><oa>free_for_read</oa></addata></record>
fulltext fulltext_linktorsrc
identifier
ispartof
issn
language eng
recordid cdi_epo_espacenet_US2022254707A1
source esp@cenet
subjects BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
SEMICONDUCTOR DEVICES
title WIREBONDABLE INTERPOSER FOR FLIP CHIP PACKAGED INTEGRATED CIRCUIT DIE
url https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-01-17T09%3A07%3A19IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-epo_EVB&rft_val_fmt=info:ofi/fmt:kev:mtx:patent&rft.genre=patent&rft.au=CHEN,%20Chihhao&rft.date=2022-08-11&rft_id=info:doi/&rft_dat=%3Cepo_EVB%3EUS2022254707A1%3C/epo_EVB%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rfr_iscdi=true