ADDER CELL AND INTEGRATED CIRCUIT INCLUDING THE SAME

A multi-height adder cell configured to receive a first input signal, a second input signal, and a carry input signal and output a sum output signal and a carry output signal, including a plurality of circuit areas, including a plurality of first gate lines to which the first input signal is applied...

Ausführliche Beschreibung

Gespeichert in:
Bibliographische Detailangaben
Hauptverfasser: Seo, Jaewoo, Jeong, Minjae, Jun, Eungchul, Kim, Yongdurk, Yang, Giyoung, Kim, Changbeom, Bae, Moogyu
Format: Patent
Sprache:eng
Schlagworte:
Online-Zugang:Volltext bestellen
Tags: Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
container_end_page
container_issue
container_start_page
container_title
container_volume
creator Seo, Jaewoo
Jeong, Minjae
Jun, Eungchul
Kim, Yongdurk
Yang, Giyoung
Kim, Changbeom
Bae, Moogyu
description A multi-height adder cell configured to receive a first input signal, a second input signal, and a carry input signal and output a sum output signal and a carry output signal, including a plurality of circuit areas, including a plurality of first gate lines to which the first input signal is applied and a plurality of second gate lines to which the second input signal is applied, wherein at least one of a first circuit area and a second circuit area is arranged in a first row, at least one of a third circuit area and a fourth circuit area is arranged in a second row parallel with the first row, and a first gate line of a circuit area arranged in the first row is aligned with a first gate line of a circuit area arranged in the second row
format Patent
fullrecord <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_US2022253283A1</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>US2022253283A1</sourcerecordid><originalsourceid>FETCH-epo_espacenet_US2022253283A13</originalsourceid><addsrcrecordid>eNrjZDBxdHFxDVJwdvXxUXD0c1Hw9AtxdQ9yDHF1UXD2DHIO9QwBCjn7hLp4-rkrhHi4KgQ7-rryMLCmJeYUp_JCaW4GZTfXEGcP3dSC_PjU4oLE5NS81JL40GAjAyMjI1NjIwtjR0Nj4lQBACyvJ9o</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>ADDER CELL AND INTEGRATED CIRCUIT INCLUDING THE SAME</title><source>esp@cenet</source><creator>Seo, Jaewoo ; Jeong, Minjae ; Jun, Eungchul ; Kim, Yongdurk ; Yang, Giyoung ; Kim, Changbeom ; Bae, Moogyu</creator><creatorcontrib>Seo, Jaewoo ; Jeong, Minjae ; Jun, Eungchul ; Kim, Yongdurk ; Yang, Giyoung ; Kim, Changbeom ; Bae, Moogyu</creatorcontrib><description>A multi-height adder cell configured to receive a first input signal, a second input signal, and a carry input signal and output a sum output signal and a carry output signal, including a plurality of circuit areas, including a plurality of first gate lines to which the first input signal is applied and a plurality of second gate lines to which the second input signal is applied, wherein at least one of a first circuit area and a second circuit area is arranged in a first row, at least one of a third circuit area and a fourth circuit area is arranged in a second row parallel with the first row, and a first gate line of a circuit area arranged in the first row is aligned with a first gate line of a circuit area arranged in the second row</description><language>eng</language><subject>BASIC ELECTRIC ELEMENTS ; BASIC ELECTRONIC CIRCUITRY ; CALCULATING ; COMPUTING ; COUNTING ; ELECTRIC DIGITAL DATA PROCESSING ; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ; ELECTRICITY ; PHYSICS ; PULSE TECHNIQUE ; SEMICONDUCTOR DEVICES</subject><creationdate>2022</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=20220811&amp;DB=EPODOC&amp;CC=US&amp;NR=2022253283A1$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,780,885,25564,76547</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=20220811&amp;DB=EPODOC&amp;CC=US&amp;NR=2022253283A1$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>Seo, Jaewoo</creatorcontrib><creatorcontrib>Jeong, Minjae</creatorcontrib><creatorcontrib>Jun, Eungchul</creatorcontrib><creatorcontrib>Kim, Yongdurk</creatorcontrib><creatorcontrib>Yang, Giyoung</creatorcontrib><creatorcontrib>Kim, Changbeom</creatorcontrib><creatorcontrib>Bae, Moogyu</creatorcontrib><title>ADDER CELL AND INTEGRATED CIRCUIT INCLUDING THE SAME</title><description>A multi-height adder cell configured to receive a first input signal, a second input signal, and a carry input signal and output a sum output signal and a carry output signal, including a plurality of circuit areas, including a plurality of first gate lines to which the first input signal is applied and a plurality of second gate lines to which the second input signal is applied, wherein at least one of a first circuit area and a second circuit area is arranged in a first row, at least one of a third circuit area and a fourth circuit area is arranged in a second row parallel with the first row, and a first gate line of a circuit area arranged in the first row is aligned with a first gate line of a circuit area arranged in the second row</description><subject>BASIC ELECTRIC ELEMENTS</subject><subject>BASIC ELECTRONIC CIRCUITRY</subject><subject>CALCULATING</subject><subject>COMPUTING</subject><subject>COUNTING</subject><subject>ELECTRIC DIGITAL DATA PROCESSING</subject><subject>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</subject><subject>ELECTRICITY</subject><subject>PHYSICS</subject><subject>PULSE TECHNIQUE</subject><subject>SEMICONDUCTOR DEVICES</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2022</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZDBxdHFxDVJwdvXxUXD0c1Hw9AtxdQ9yDHF1UXD2DHIO9QwBCjn7hLp4-rkrhHi4KgQ7-rryMLCmJeYUp_JCaW4GZTfXEGcP3dSC_PjU4oLE5NS81JL40GAjAyMjI1NjIwtjR0Nj4lQBACyvJ9o</recordid><startdate>20220811</startdate><enddate>20220811</enddate><creator>Seo, Jaewoo</creator><creator>Jeong, Minjae</creator><creator>Jun, Eungchul</creator><creator>Kim, Yongdurk</creator><creator>Yang, Giyoung</creator><creator>Kim, Changbeom</creator><creator>Bae, Moogyu</creator><scope>EVB</scope></search><sort><creationdate>20220811</creationdate><title>ADDER CELL AND INTEGRATED CIRCUIT INCLUDING THE SAME</title><author>Seo, Jaewoo ; Jeong, Minjae ; Jun, Eungchul ; Kim, Yongdurk ; Yang, Giyoung ; Kim, Changbeom ; Bae, Moogyu</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_US2022253283A13</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>2022</creationdate><topic>BASIC ELECTRIC ELEMENTS</topic><topic>BASIC ELECTRONIC CIRCUITRY</topic><topic>CALCULATING</topic><topic>COMPUTING</topic><topic>COUNTING</topic><topic>ELECTRIC DIGITAL DATA PROCESSING</topic><topic>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</topic><topic>ELECTRICITY</topic><topic>PHYSICS</topic><topic>PULSE TECHNIQUE</topic><topic>SEMICONDUCTOR DEVICES</topic><toplevel>online_resources</toplevel><creatorcontrib>Seo, Jaewoo</creatorcontrib><creatorcontrib>Jeong, Minjae</creatorcontrib><creatorcontrib>Jun, Eungchul</creatorcontrib><creatorcontrib>Kim, Yongdurk</creatorcontrib><creatorcontrib>Yang, Giyoung</creatorcontrib><creatorcontrib>Kim, Changbeom</creatorcontrib><creatorcontrib>Bae, Moogyu</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Seo, Jaewoo</au><au>Jeong, Minjae</au><au>Jun, Eungchul</au><au>Kim, Yongdurk</au><au>Yang, Giyoung</au><au>Kim, Changbeom</au><au>Bae, Moogyu</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>ADDER CELL AND INTEGRATED CIRCUIT INCLUDING THE SAME</title><date>2022-08-11</date><risdate>2022</risdate><abstract>A multi-height adder cell configured to receive a first input signal, a second input signal, and a carry input signal and output a sum output signal and a carry output signal, including a plurality of circuit areas, including a plurality of first gate lines to which the first input signal is applied and a plurality of second gate lines to which the second input signal is applied, wherein at least one of a first circuit area and a second circuit area is arranged in a first row, at least one of a third circuit area and a fourth circuit area is arranged in a second row parallel with the first row, and a first gate line of a circuit area arranged in the first row is aligned with a first gate line of a circuit area arranged in the second row</abstract><oa>free_for_read</oa></addata></record>
fulltext fulltext_linktorsrc
identifier
ispartof
issn
language eng
recordid cdi_epo_espacenet_US2022253283A1
source esp@cenet
subjects BASIC ELECTRIC ELEMENTS
BASIC ELECTRONIC CIRCUITRY
CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
PHYSICS
PULSE TECHNIQUE
SEMICONDUCTOR DEVICES
title ADDER CELL AND INTEGRATED CIRCUIT INCLUDING THE SAME
url https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-01-01T21%3A04%3A20IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-epo_EVB&rft_val_fmt=info:ofi/fmt:kev:mtx:patent&rft.genre=patent&rft.au=Seo,%20Jaewoo&rft.date=2022-08-11&rft_id=info:doi/&rft_dat=%3Cepo_EVB%3EUS2022253283A1%3C/epo_EVB%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rfr_iscdi=true