DYNAMICALLY GATED SEARCH LINES FOR LOW-POWER MULTI-STAGE CONTENT ADDRESSABLE MEMORY

DYNAMICALLY GATED SEARCH LINES FOR LOW-POWER MULTI-STAGE CONTENT ADDRESSABLE MEMORY

A content addressable memory (CAM) device includes multiple CAM sub-banks Each CAM sub-bank includes an array of CAM cells arranged in rows and columns and partitioned into a first stage and a second stage along a column dimension. Each CAM sub-bank further includes first-stage match lines (MLs), fi...

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Hauptverfasser: Kumar, Sushil, Deshpande, Chetan, Garg, Ritesh, Jedhe, Gajanan Sahebrao, Narvekar, Gaurang Prabhakar
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INFORMATION STORAGE
PHYSICS
STATIC STORES
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creator Kumar, Sushil
Deshpande, Chetan
Garg, Ritesh
Jedhe, Gajanan Sahebrao
Narvekar, Gaurang Prabhakar
description A content addressable memory (CAM) device includes multiple CAM sub-banks Each CAM sub-bank includes an array of CAM cells arranged in rows and columns and partitioned into a first stage and a second stage along a column dimension. Each CAM sub-bank further includes first-stage match lines (MLs), first-stage search line (SL) pairs, second-stage MLs, and second-stage SL pairs. Each second-stage SL pair is coupled to a column of CAM cells in the second stage and is gated by an SL enable (SL_EN signal). Each CAM sub-bank further includes a circuit operative to receive all of the first-stage MLs as input and de-assert the SL_EN signal when none of the first-stage MLs indicate a match. De-assertion of the SL_EN signal blocks a second portion search key from being provided to the second-stage SL pairs.
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STATIC STORES
title DYNAMICALLY GATED SEARCH LINES FOR LOW-POWER MULTI-STAGE CONTENT ADDRESSABLE MEMORY
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