Conductive Interconnects and Methods of Forming Conductive Interconnects

Some embodiments include an integrated assembly having an interconnect over a first conductive structure and coupled with the first conductive structure. The interconnect includes a conductive core. The conductive core has a slender upper region and a wide lower region. The upper region joins to the...

Ausführliche Beschreibung

Gespeichert in:
Bibliographische Detailangaben
Hauptverfasser: Kewley, David A, Ahmed, Raju, Lugani, Gurpreet, Speetjens, Frank, Pratt, Dave, Sung, Yung-Ta
Format: Patent
Sprache:eng
Schlagworte:
Online-Zugang:Volltext bestellen
Tags: Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
container_end_page
container_issue
container_start_page
container_title
container_volume
creator Kewley, David A
Ahmed, Raju
Lugani, Gurpreet
Speetjens, Frank
Pratt, Dave
Sung, Yung-Ta
description Some embodiments include an integrated assembly having an interconnect over a first conductive structure and coupled with the first conductive structure. The interconnect includes a conductive core. The conductive core has a slender upper region and a wide lower region. The upper region joins to the lower region at a step. A liner laterally surrounds the lower region of the conductive core. The liner has an upper surface which is substantially coplanar with the step. An insulative collar is over and directly against both an upper surface of the step and the upper surface of the liner. The insulative collar laterally surrounds and directly contacts the slender upper region. A second conductive structure is over and directly against a region of the insulative collar, and is over and directly against an upper surface of the slender upper region. Some embodiments include methods of forming integrated assemblies.
format Patent
fullrecord <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_US2022199123A1</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>US2022199123A1</sourcerecordid><originalsourceid>FETCH-epo_espacenet_US2022199123A13</originalsourceid><addsrcrecordid>eNrjZPBwzs9LKU0uySxLVfDMK0ktSs7Py0tNLilWSMxLUfBNLcnITylWyE9TcMsvys3MS1fApZ6HgTUtMac4lRdKczMou7mGOHvophbkx6cWFyQmp-allsSHBhsZGBkZWloaGhk7GhoTpwoAnrE1lQ</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>Conductive Interconnects and Methods of Forming Conductive Interconnects</title><source>esp@cenet</source><creator>Kewley, David A ; Ahmed, Raju ; Lugani, Gurpreet ; Speetjens, Frank ; Pratt, Dave ; Sung, Yung-Ta</creator><creatorcontrib>Kewley, David A ; Ahmed, Raju ; Lugani, Gurpreet ; Speetjens, Frank ; Pratt, Dave ; Sung, Yung-Ta</creatorcontrib><description>Some embodiments include an integrated assembly having an interconnect over a first conductive structure and coupled with the first conductive structure. The interconnect includes a conductive core. The conductive core has a slender upper region and a wide lower region. The upper region joins to the lower region at a step. A liner laterally surrounds the lower region of the conductive core. The liner has an upper surface which is substantially coplanar with the step. An insulative collar is over and directly against both an upper surface of the step and the upper surface of the liner. The insulative collar laterally surrounds and directly contacts the slender upper region. A second conductive structure is over and directly against a region of the insulative collar, and is over and directly against an upper surface of the slender upper region. Some embodiments include methods of forming integrated assemblies.</description><language>eng</language><subject>BASIC ELECTRIC ELEMENTS ; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ; ELECTRICITY ; INFORMATION STORAGE ; PHYSICS ; SEMICONDUCTOR DEVICES ; STATIC STORES</subject><creationdate>2022</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=20220623&amp;DB=EPODOC&amp;CC=US&amp;NR=2022199123A1$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,780,885,25563,76318</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=20220623&amp;DB=EPODOC&amp;CC=US&amp;NR=2022199123A1$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>Kewley, David A</creatorcontrib><creatorcontrib>Ahmed, Raju</creatorcontrib><creatorcontrib>Lugani, Gurpreet</creatorcontrib><creatorcontrib>Speetjens, Frank</creatorcontrib><creatorcontrib>Pratt, Dave</creatorcontrib><creatorcontrib>Sung, Yung-Ta</creatorcontrib><title>Conductive Interconnects and Methods of Forming Conductive Interconnects</title><description>Some embodiments include an integrated assembly having an interconnect over a first conductive structure and coupled with the first conductive structure. The interconnect includes a conductive core. The conductive core has a slender upper region and a wide lower region. The upper region joins to the lower region at a step. A liner laterally surrounds the lower region of the conductive core. The liner has an upper surface which is substantially coplanar with the step. An insulative collar is over and directly against both an upper surface of the step and the upper surface of the liner. The insulative collar laterally surrounds and directly contacts the slender upper region. A second conductive structure is over and directly against a region of the insulative collar, and is over and directly against an upper surface of the slender upper region. Some embodiments include methods of forming integrated assemblies.</description><subject>BASIC ELECTRIC ELEMENTS</subject><subject>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</subject><subject>ELECTRICITY</subject><subject>INFORMATION STORAGE</subject><subject>PHYSICS</subject><subject>SEMICONDUCTOR DEVICES</subject><subject>STATIC STORES</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2022</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZPBwzs9LKU0uySxLVfDMK0ktSs7Py0tNLilWSMxLUfBNLcnITylWyE9TcMsvys3MS1fApZ6HgTUtMac4lRdKczMou7mGOHvophbkx6cWFyQmp-allsSHBhsZGBkZWloaGhk7GhoTpwoAnrE1lQ</recordid><startdate>20220623</startdate><enddate>20220623</enddate><creator>Kewley, David A</creator><creator>Ahmed, Raju</creator><creator>Lugani, Gurpreet</creator><creator>Speetjens, Frank</creator><creator>Pratt, Dave</creator><creator>Sung, Yung-Ta</creator><scope>EVB</scope></search><sort><creationdate>20220623</creationdate><title>Conductive Interconnects and Methods of Forming Conductive Interconnects</title><author>Kewley, David A ; Ahmed, Raju ; Lugani, Gurpreet ; Speetjens, Frank ; Pratt, Dave ; Sung, Yung-Ta</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_US2022199123A13</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>2022</creationdate><topic>BASIC ELECTRIC ELEMENTS</topic><topic>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</topic><topic>ELECTRICITY</topic><topic>INFORMATION STORAGE</topic><topic>PHYSICS</topic><topic>SEMICONDUCTOR DEVICES</topic><topic>STATIC STORES</topic><toplevel>online_resources</toplevel><creatorcontrib>Kewley, David A</creatorcontrib><creatorcontrib>Ahmed, Raju</creatorcontrib><creatorcontrib>Lugani, Gurpreet</creatorcontrib><creatorcontrib>Speetjens, Frank</creatorcontrib><creatorcontrib>Pratt, Dave</creatorcontrib><creatorcontrib>Sung, Yung-Ta</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Kewley, David A</au><au>Ahmed, Raju</au><au>Lugani, Gurpreet</au><au>Speetjens, Frank</au><au>Pratt, Dave</au><au>Sung, Yung-Ta</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>Conductive Interconnects and Methods of Forming Conductive Interconnects</title><date>2022-06-23</date><risdate>2022</risdate><abstract>Some embodiments include an integrated assembly having an interconnect over a first conductive structure and coupled with the first conductive structure. The interconnect includes a conductive core. The conductive core has a slender upper region and a wide lower region. The upper region joins to the lower region at a step. A liner laterally surrounds the lower region of the conductive core. The liner has an upper surface which is substantially coplanar with the step. An insulative collar is over and directly against both an upper surface of the step and the upper surface of the liner. The insulative collar laterally surrounds and directly contacts the slender upper region. A second conductive structure is over and directly against a region of the insulative collar, and is over and directly against an upper surface of the slender upper region. Some embodiments include methods of forming integrated assemblies.</abstract><oa>free_for_read</oa></addata></record>
fulltext fulltext_linktorsrc
identifier
ispartof
issn
language eng
recordid cdi_epo_espacenet_US2022199123A1
source esp@cenet
subjects BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
INFORMATION STORAGE
PHYSICS
SEMICONDUCTOR DEVICES
STATIC STORES
title Conductive Interconnects and Methods of Forming Conductive Interconnects
url https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-01-13T00%3A06%3A23IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-epo_EVB&rft_val_fmt=info:ofi/fmt:kev:mtx:patent&rft.genre=patent&rft.au=Kewley,%20David%20A&rft.date=2022-06-23&rft_id=info:doi/&rft_dat=%3Cepo_EVB%3EUS2022199123A1%3C/epo_EVB%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rfr_iscdi=true