LOW POWER POWER-UP RESET OUTPUT DRIVER

LOW POWER POWER-UP RESET OUTPUT DRIVER

Embodiments of the disclosure provide an input output (IO) structure in which complimentary nodes of a level shifter are utilized to logically block the output of the IO structure from switching until both power supplies to the IO structure are powered up. An illustrative level shifter includes: a c...

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Hauptverfasser: Tran, Dzung T, Ahmed, Shibly S
Format: Patent
Sprache:eng
Schlagworte:
BASIC ELECTRONIC CIRCUITRY
ELECTRICITY
PULSE TECHNIQUE
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creator Tran, Dzung T
Ahmed, Shibly S
description Embodiments of the disclosure provide an input output (IO) structure in which complimentary nodes of a level shifter are utilized to logically block the output of the IO structure from switching until both power supplies to the IO structure are powered up. An illustrative level shifter includes: a cross-coupled pair of PFETs configured to output complimentary voltage values at a first node and a second node; a control circuit configured to select which of the complementary voltage values are output to the first node and second node; a logic inverter having an input coupled to the first node and an output coupled to a third node; and a NAND gate having inputs coupled to the second node and third node and that generates a level shifted output.
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fullrecord <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_US2022182058A1</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>US2022182058A1</sourcerecordid><originalsourceid>FETCH-epo_espacenet_US2022182058A13</originalsourceid><addsrcrecordid>eNrjZFDz8Q9XCPAPdw2CkLqhAQpBrsGuIQr-oSEBoSEKLkGeYa5BPAysaYk5xam8UJqbQdnNNcTZQze1ID8-tbggMTk1L7UkPjTYyMDIyNDCyMDUwtHQmDhVAGzQJLs</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>LOW POWER POWER-UP RESET OUTPUT DRIVER</title><source>esp@cenet</source><creator>Tran, Dzung T ; Ahmed, Shibly S</creator><creatorcontrib>Tran, Dzung T ; Ahmed, Shibly S</creatorcontrib><description>Embodiments of the disclosure provide an input output (IO) structure in which complimentary nodes of a level shifter are utilized to logically block the output of the IO structure from switching until both power supplies to the IO structure are powered up. An illustrative level shifter includes: a cross-coupled pair of PFETs configured to output complimentary voltage values at a first node and a second node; a control circuit configured to select which of the complementary voltage values are output to the first node and second node; a logic inverter having an input coupled to the first node and an output coupled to a third node; and a NAND gate having inputs coupled to the second node and third node and that generates a level shifted output.</description><language>eng</language><subject>BASIC ELECTRONIC CIRCUITRY ; ELECTRICITY ; PULSE TECHNIQUE</subject><creationdate>2022</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=20220609&amp;DB=EPODOC&amp;CC=US&amp;NR=2022182058A1$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,780,885,25564,76547</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=20220609&amp;DB=EPODOC&amp;CC=US&amp;NR=2022182058A1$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>Tran, Dzung T</creatorcontrib><creatorcontrib>Ahmed, Shibly S</creatorcontrib><title>LOW POWER POWER-UP RESET OUTPUT DRIVER</title><description>Embodiments of the disclosure provide an input output (IO) structure in which complimentary nodes of a level shifter are utilized to logically block the output of the IO structure from switching until both power supplies to the IO structure are powered up. An illustrative level shifter includes: a cross-coupled pair of PFETs configured to output complimentary voltage values at a first node and a second node; a control circuit configured to select which of the complementary voltage values are output to the first node and second node; a logic inverter having an input coupled to the first node and an output coupled to a third node; and a NAND gate having inputs coupled to the second node and third node and that generates a level shifted output.</description><subject>BASIC ELECTRONIC CIRCUITRY</subject><subject>ELECTRICITY</subject><subject>PULSE TECHNIQUE</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2022</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZFDz8Q9XCPAPdw2CkLqhAQpBrsGuIQr-oSEBoSEKLkGeYa5BPAysaYk5xam8UJqbQdnNNcTZQze1ID8-tbggMTk1L7UkPjTYyMDIyNDCyMDUwtHQmDhVAGzQJLs</recordid><startdate>20220609</startdate><enddate>20220609</enddate><creator>Tran, Dzung T</creator><creator>Ahmed, Shibly S</creator><scope>EVB</scope></search><sort><creationdate>20220609</creationdate><title>LOW POWER POWER-UP RESET OUTPUT DRIVER</title><author>Tran, Dzung T ; Ahmed, Shibly S</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_US2022182058A13</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>2022</creationdate><topic>BASIC ELECTRONIC CIRCUITRY</topic><topic>ELECTRICITY</topic><topic>PULSE TECHNIQUE</topic><toplevel>online_resources</toplevel><creatorcontrib>Tran, Dzung T</creatorcontrib><creatorcontrib>Ahmed, Shibly S</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Tran, Dzung T</au><au>Ahmed, Shibly S</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>LOW POWER POWER-UP RESET OUTPUT DRIVER</title><date>2022-06-09</date><risdate>2022</risdate><abstract>Embodiments of the disclosure provide an input output (IO) structure in which complimentary nodes of a level shifter are utilized to logically block the output of the IO structure from switching until both power supplies to the IO structure are powered up. An illustrative level shifter includes: a cross-coupled pair of PFETs configured to output complimentary voltage values at a first node and a second node; a control circuit configured to select which of the complementary voltage values are output to the first node and second node; a logic inverter having an input coupled to the first node and an output coupled to a third node; and a NAND gate having inputs coupled to the second node and third node and that generates a level shifted output.</abstract><oa>free_for_read</oa></addata></record>
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subjects BASIC ELECTRONIC CIRCUITRY
ELECTRICITY
PULSE TECHNIQUE
title LOW POWER POWER-UP RESET OUTPUT DRIVER
url https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2024-12-25T23%3A23%3A00IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-epo_EVB&rft_val_fmt=info:ofi/fmt:kev:mtx:patent&rft.genre=patent&rft.au=Tran,%20Dzung%20T&rft.date=2022-06-09&rft_id=info:doi/&rft_dat=%3Cepo_EVB%3EUS2022182058A1%3C/epo_EVB%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rfr_iscdi=true