METHOD FOR MIGRATING CPU STATE FROM AN INOPERABLE CORE TO A SPARE CORE
An apparatus is disclosed in which the apparatus may include a plurality of cores, including a first core, a second core and a third core, and circuitry coupled to the first core. The first core may be configured to process a plurality of instructions. The circuitry may be may be configured to detec...
Gespeichert in:
| Hauptverfasser: | , , , |
|---|---|
| Format: | Patent |
| Sprache: | eng |
| Schlagworte: | |
| Online-Zugang: | Volltext bestellen |
| Tags: |
Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
|
| container_end_page | |
|---|---|
| container_issue | |
| container_start_page | |
| container_title | |
| container_volume | |
| creator | Vahidsafa, Ali Onufer, Gregory Jordan, Paul Lewis, James |
| description | An apparatus is disclosed in which the apparatus may include a plurality of cores, including a first core, a second core and a third core, and circuitry coupled to the first core. The first core may be configured to process a plurality of instructions. The circuitry may be may be configured to detect that the first core stopped committing a subset of the plurality of instructions, and to send an indication to the second core that the first core stopped committing the subset. The second core may be configured to disable the first core from further processing instructions of the subset responsive to receiving the indication, and to copy data from the first core to a third core responsive to disabling the first core. The third core may be configured to resume processing the subset dependent upon the data. |
| format | Patent |
| fullrecord | <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_US2022156075A1</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>US2022156075A1</sourcerecordid><originalsourceid>FETCH-epo_espacenet_US2022156075A13</originalsourceid><addsrcrecordid>eNrjZHDzdQ3x8HdRcPMPUvD1dA9yDPH0c1dwDghVCA5xDHFVcAvy91Vw9FPw9PMPcA1ydPJxVXD2D3JVCPFXcFQIDnAMgvB5GFjTEnOKU3mhNDeDsptriLOHbmpBfnxqcUFicmpeakl8aLCRgZGRoamZgbmpo6ExcaoAHUwspQ</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>METHOD FOR MIGRATING CPU STATE FROM AN INOPERABLE CORE TO A SPARE CORE</title><source>esp@cenet</source><creator>Vahidsafa, Ali ; Onufer, Gregory ; Jordan, Paul ; Lewis, James</creator><creatorcontrib>Vahidsafa, Ali ; Onufer, Gregory ; Jordan, Paul ; Lewis, James</creatorcontrib><description>An apparatus is disclosed in which the apparatus may include a plurality of cores, including a first core, a second core and a third core, and circuitry coupled to the first core. The first core may be configured to process a plurality of instructions. The circuitry may be may be configured to detect that the first core stopped committing a subset of the plurality of instructions, and to send an indication to the second core that the first core stopped committing the subset. The second core may be configured to disable the first core from further processing instructions of the subset responsive to receiving the indication, and to copy data from the first core to a third core responsive to disabling the first core. The third core may be configured to resume processing the subset dependent upon the data.</description><language>eng</language><subject>CALCULATING ; COMPUTING ; COUNTING ; ELECTRIC DIGITAL DATA PROCESSING ; PHYSICS</subject><creationdate>2022</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20220519&DB=EPODOC&CC=US&NR=2022156075A1$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,776,881,25542,76289</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20220519&DB=EPODOC&CC=US&NR=2022156075A1$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>Vahidsafa, Ali</creatorcontrib><creatorcontrib>Onufer, Gregory</creatorcontrib><creatorcontrib>Jordan, Paul</creatorcontrib><creatorcontrib>Lewis, James</creatorcontrib><title>METHOD FOR MIGRATING CPU STATE FROM AN INOPERABLE CORE TO A SPARE CORE</title><description>An apparatus is disclosed in which the apparatus may include a plurality of cores, including a first core, a second core and a third core, and circuitry coupled to the first core. The first core may be configured to process a plurality of instructions. The circuitry may be may be configured to detect that the first core stopped committing a subset of the plurality of instructions, and to send an indication to the second core that the first core stopped committing the subset. The second core may be configured to disable the first core from further processing instructions of the subset responsive to receiving the indication, and to copy data from the first core to a third core responsive to disabling the first core. The third core may be configured to resume processing the subset dependent upon the data.</description><subject>CALCULATING</subject><subject>COMPUTING</subject><subject>COUNTING</subject><subject>ELECTRIC DIGITAL DATA PROCESSING</subject><subject>PHYSICS</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2022</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZHDzdQ3x8HdRcPMPUvD1dA9yDPH0c1dwDghVCA5xDHFVcAvy91Vw9FPw9PMPcA1ydPJxVXD2D3JVCPFXcFQIDnAMgvB5GFjTEnOKU3mhNDeDsptriLOHbmpBfnxqcUFicmpeakl8aLCRgZGRoamZgbmpo6ExcaoAHUwspQ</recordid><startdate>20220519</startdate><enddate>20220519</enddate><creator>Vahidsafa, Ali</creator><creator>Onufer, Gregory</creator><creator>Jordan, Paul</creator><creator>Lewis, James</creator><scope>EVB</scope></search><sort><creationdate>20220519</creationdate><title>METHOD FOR MIGRATING CPU STATE FROM AN INOPERABLE CORE TO A SPARE CORE</title><author>Vahidsafa, Ali ; Onufer, Gregory ; Jordan, Paul ; Lewis, James</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_US2022156075A13</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>2022</creationdate><topic>CALCULATING</topic><topic>COMPUTING</topic><topic>COUNTING</topic><topic>ELECTRIC DIGITAL DATA PROCESSING</topic><topic>PHYSICS</topic><toplevel>online_resources</toplevel><creatorcontrib>Vahidsafa, Ali</creatorcontrib><creatorcontrib>Onufer, Gregory</creatorcontrib><creatorcontrib>Jordan, Paul</creatorcontrib><creatorcontrib>Lewis, James</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Vahidsafa, Ali</au><au>Onufer, Gregory</au><au>Jordan, Paul</au><au>Lewis, James</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>METHOD FOR MIGRATING CPU STATE FROM AN INOPERABLE CORE TO A SPARE CORE</title><date>2022-05-19</date><risdate>2022</risdate><abstract>An apparatus is disclosed in which the apparatus may include a plurality of cores, including a first core, a second core and a third core, and circuitry coupled to the first core. The first core may be configured to process a plurality of instructions. The circuitry may be may be configured to detect that the first core stopped committing a subset of the plurality of instructions, and to send an indication to the second core that the first core stopped committing the subset. The second core may be configured to disable the first core from further processing instructions of the subset responsive to receiving the indication, and to copy data from the first core to a third core responsive to disabling the first core. The third core may be configured to resume processing the subset dependent upon the data.</abstract><oa>free_for_read</oa></addata></record> |
| fulltext | fulltext_linktorsrc |
| identifier | |
| ispartof | |
| issn | |
| language | eng |
| recordid | cdi_epo_espacenet_US2022156075A1 |
| source | esp@cenet |
| subjects | CALCULATING COMPUTING COUNTING ELECTRIC DIGITAL DATA PROCESSING PHYSICS |
| title | METHOD FOR MIGRATING CPU STATE FROM AN INOPERABLE CORE TO A SPARE CORE |
| url | https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-02-08T21%3A24%3A19IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-epo_EVB&rft_val_fmt=info:ofi/fmt:kev:mtx:patent&rft.genre=patent&rft.au=Vahidsafa,%20Ali&rft.date=2022-05-19&rft_id=info:doi/&rft_dat=%3Cepo_EVB%3EUS2022156075A1%3C/epo_EVB%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rfr_iscdi=true |