MEMORIES FOR CALIBRATING SENSING OF MEMORY CELL DATA STATES

Memory might include a controller configured to determine, for each sense circuit of a plurality of sense circuits, a respective plurality of first logic levels for that sense circuit while capacitively coupling a respective plurality of voltage levels to its respective sense node, to determine a pa...

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Hauptverfasser:	Valeri, Gianfranco, Moschiano, Violante, Di-Francesco, Walter
Format:	Patent
Sprache:	eng
Schlagworte:	INFORMATION STORAGE PHYSICS STATIC STORES
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creator	Valeri, Gianfranco Moschiano, Violante Di-Francesco, Walter
description	Memory might include a controller configured to determine, for each sense circuit of a plurality of sense circuits, a respective plurality of first logic levels for that sense circuit while capacitively coupling a respective plurality of voltage levels to its respective sense node, to determine a particular voltage level in response to each respective plurality of first logic levels for the plurality of sense circuits and their respective plurality of voltage levels, and to determine, for each sense circuit of the plurality of sense circuits, a respective second logic level for that sense circuit while capacitively coupling the particular voltage level to its respective sense node.
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Moschiano, Violante ; Di-Francesco, Walter</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_US2022148661A13</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>2022</creationdate><topic>INFORMATION STORAGE</topic><topic>PHYSICS</topic><topic>STATIC STORES</topic><toplevel>online_resources</toplevel><creatorcontrib>Valeri, Gianfranco</creatorcontrib><creatorcontrib>Moschiano, Violante</creatorcontrib><creatorcontrib>Di-Francesco, Walter</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Valeri, Gianfranco</au><au>Moschiano, Violante</au><au>Di-Francesco, Walter</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>MEMORIES FOR CALIBRATING SENSING OF MEMORY CELL DATA STATES</title><date>2022-05-12</date><risdate>2022</risdate><abstract>Memory might include a controller configured to determine, for each sense circuit of a plurality of sense circuits, a respective plurality of first logic levels for that sense circuit while capacitively coupling a respective plurality of voltage levels to its respective sense node, to determine a particular voltage level in response to each respective plurality of first logic levels for the plurality of sense circuits and their respective plurality of voltage levels, and to determine, for each sense circuit of the plurality of sense circuits, a respective second logic level for that sense circuit while capacitively coupling the particular voltage level to its respective sense node.</abstract><oa>free_for_read</oa></addata></record>
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subjects	INFORMATION STORAGE PHYSICS STATIC STORES
title	MEMORIES FOR CALIBRATING SENSING OF MEMORY CELL DATA STATES
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