MEMORY DEVICE CAPABLE OF OUTPUTTING FAIL DATA IN PARALLEL BIT TEST AND MEMORY SYSTEM INCLUDING THE MEMORY DEVICE

A memory device includes a memory cell array and a test controller. The memory cell array includes a plurality of memory cells, where the memory cell array is divided into multiple regions. The test controller is configured to perform a parallel bit test (PBT) on the plurality of memory cells, where...

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Bibliographische Detailangaben

Hauptverfasser:	SHIN, WONJAE, KIM, DAEJEONG, KIM, DOHAN, CHOI, INSU, KIM, NAMHYUNG, SEO, DEOKHO
Format:	Patent
Sprache:	eng
Schlagworte:	CALCULATING COMPUTING COUNTING ELECTRIC DIGITAL DATA PROCESSING INFORMATION STORAGE PHYSICS STATIC STORES
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