WAFER STRUCTURE
A wafer structure is disclosed and includes a chip substrate and a plurality of inkjet chips. The chip substrate is a silicon substrate which is fabricated by a semiconductor process on a wafer of at least 12 inches. The plurality of inkjet chips include at least one first inkjet chip and at least o...
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| creator | Han, Yung-Lung Tai, Hsien-Chung Huang, Chi-Feng Mou, Hao-Jan Chang, Ying-Lun |
| description | A wafer structure is disclosed and includes a chip substrate and a plurality of inkjet chips. The chip substrate is a silicon substrate which is fabricated by a semiconductor process on a wafer of at least 12 inches. The plurality of inkjet chips include at least one first inkjet chip and at least one second inkjet chip. The plurality of inkjet chips are directly formed on the chip substrate by the semiconductor process, respectively, and diced into the at least one first inkjet chip and the at least one second inkjet chip, to be implemented for inkjet printing. |
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The chip substrate is a silicon substrate which is fabricated by a semiconductor process on a wafer of at least 12 inches. The plurality of inkjet chips include at least one first inkjet chip and at least one second inkjet chip. The plurality of inkjet chips are directly formed on the chip substrate by the semiconductor process, respectively, and diced into the at least one first inkjet chip and the at least one second inkjet chip, to be implemented for inkjet printing.</description><language>eng</language><subject>CORRECTION OF TYPOGRAPHICAL ERRORS ; i.e. MECHANISMS PRINTING OTHERWISE THAN FROM A FORME ; LINING MACHINES ; PERFORMING OPERATIONS ; PRINTING ; SELECTIVE PRINTING MECHANISMS ; STAMPS ; TRANSPORTING ; TYPEWRITERS</subject><creationdate>2022</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20220505&DB=EPODOC&CC=US&NR=2022134751A1$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,776,881,25543,76293</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20220505&DB=EPODOC&CC=US&NR=2022134751A1$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>Han, Yung-Lung</creatorcontrib><creatorcontrib>Tai, Hsien-Chung</creatorcontrib><creatorcontrib>Huang, Chi-Feng</creatorcontrib><creatorcontrib>Mou, Hao-Jan</creatorcontrib><creatorcontrib>Chang, Ying-Lun</creatorcontrib><title>WAFER STRUCTURE</title><description>A wafer structure is disclosed and includes a chip substrate and a plurality of inkjet chips. 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| subjects | CORRECTION OF TYPOGRAPHICAL ERRORS i.e. MECHANISMS PRINTING OTHERWISE THAN FROM A FORME LINING MACHINES PERFORMING OPERATIONS PRINTING SELECTIVE PRINTING MECHANISMS STAMPS TRANSPORTING TYPEWRITERS |
| title | WAFER STRUCTURE |
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