MEMORY DEVICE AND OPERATING METHOD THEREOF

A memory device includes a page buffer circuit including a plurality of page buffer stages each including a plurality of page buffers. The memory device also includes a control circuit configured to generate page buffer control signals for controlling the plurality of page buffers. The control circuit is also configured to probe each of a plurality of page buffer control signal groups configured with the page buffer control signals through a probing path corresponding to each of the plurality of page buffer control signal groups.