MICROPROCESSOR, AND OPERATION METHOD THEREFOR

MICROPROCESSOR, AND OPERATION METHOD THEREFOR

A microprocessor that includes a plurality of instruction sets and has a reduced code size is provided.A microprocessor includes a plurality of instruction sets and executes a program while switching instruction sets on the basis of an instruction set switching bit that is included in an instruction...

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1. Verfasser: NAKAMURA, YUUICHI
Format: Patent
Sprache:eng
Schlagworte:
CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
PHYSICS
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creator NAKAMURA, YUUICHI
description A microprocessor that includes a plurality of instruction sets and has a reduced code size is provided.A microprocessor includes a plurality of instruction sets and executes a program while switching instruction sets on the basis of an instruction set switching bit that is included in an instruction code having been read in and represents an instruction set that should be executed next at the time of execution of the program. Each instruction set includes a set of collected instruction codes that are to be used when each intermediate language instruction that is classified in accordance with a process content is executed. Then, for each instruction set, instruction sets that are possible to be selected and should be executed next are limited in an instruction code.
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subjects CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
PHYSICS
title MICROPROCESSOR, AND OPERATION METHOD THEREFOR
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