MULTI-TILE ARCHITECTURE FOR GRAPHICS OPERATIONS
Embodiments are generally directed to a multi-tile architecture for graphics operations. An embodiment of an apparatus includes a multi-tile architecture for graphics operations including a multi-tile graphics processor, the multi-tile processor includes one or more dies; multiple processor tiles in...
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| creator | Anantaraman, Aravindh Ould-Ahmed-Vall, Elmoustapha Tangri, Saurabh George, Varghese Insko, Brent E Ranganathan, Vasanth Appu, Abhishek R Panneer, Selvakumar Striramassarma, Lakshminarayanan Prasoonkumar, Surti Cooray, Niranjan Koker, Altug Ashbaugh, Ben Ray, Joydeep Sinha, Kamal Janus, Scott Hunter, Arthur |
| description | Embodiments are generally directed to a multi-tile architecture for graphics operations. An embodiment of an apparatus includes a multi-tile architecture for graphics operations including a multi-tile graphics processor, the multi-tile processor includes one or more dies; multiple processor tiles installed on the one or more dies; and a structure to interconnect the processor tiles on the one or more dies, wherein the structure to enable communications between processor tiles the processor tiles. |
| format | Patent |
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An embodiment of an apparatus includes a multi-tile architecture for graphics operations including a multi-tile graphics processor, the multi-tile processor includes one or more dies; multiple processor tiles installed on the one or more dies; and a structure to interconnect the processor tiles on the one or more dies, wherein the structure to enable communications between processor tiles the processor tiles.</description><language>eng</language><subject>CALCULATING ; COMPUTING ; COUNTING ; ELECTRIC DIGITAL DATA PROCESSING ; PHYSICS</subject><creationdate>2022</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20220407&DB=EPODOC&CC=US&NR=2022107914A1$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,780,885,25564,76547</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20220407&DB=EPODOC&CC=US&NR=2022107914A1$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>Anantaraman, Aravindh</creatorcontrib><creatorcontrib>Ould-Ahmed-Vall, Elmoustapha</creatorcontrib><creatorcontrib>Tangri, Saurabh</creatorcontrib><creatorcontrib>George, Varghese</creatorcontrib><creatorcontrib>Insko, Brent E</creatorcontrib><creatorcontrib>Ranganathan, Vasanth</creatorcontrib><creatorcontrib>Appu, Abhishek R</creatorcontrib><creatorcontrib>Panneer, Selvakumar</creatorcontrib><creatorcontrib>Striramassarma, Lakshminarayanan</creatorcontrib><creatorcontrib>Prasoonkumar, Surti</creatorcontrib><creatorcontrib>Cooray, Niranjan</creatorcontrib><creatorcontrib>Koker, Altug</creatorcontrib><creatorcontrib>Ashbaugh, Ben</creatorcontrib><creatorcontrib>Ray, Joydeep</creatorcontrib><creatorcontrib>Sinha, Kamal</creatorcontrib><creatorcontrib>Janus, Scott</creatorcontrib><creatorcontrib>Hunter, Arthur</creatorcontrib><title>MULTI-TILE ARCHITECTURE FOR GRAPHICS OPERATIONS</title><description>Embodiments are generally directed to a multi-tile architecture for graphics operations. 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An embodiment of an apparatus includes a multi-tile architecture for graphics operations including a multi-tile graphics processor, the multi-tile processor includes one or more dies; multiple processor tiles installed on the one or more dies; and a structure to interconnect the processor tiles on the one or more dies, wherein the structure to enable communications between processor tiles the processor tiles.</abstract><oa>free_for_read</oa></addata></record> |
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| language | eng |
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| subjects | CALCULATING COMPUTING COUNTING ELECTRIC DIGITAL DATA PROCESSING PHYSICS |
| title | MULTI-TILE ARCHITECTURE FOR GRAPHICS OPERATIONS |
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