Cluster Intralayer Safety Mechanism In An Artificial Neural Network Processor

Novel and useful system and methods of several functional safety mechanisms for use in an artificial neural network (ANN) processor. The mechanisms can be deployed individually or in combination to provide a desired level of safety in neural networks. Multiple strategies are applied involving redund...

Ausführliche Beschreibung

Gespeichert in:
Bibliographische Detailangaben
Hauptverfasser: Adelstein, Yuval, Chibotero, Daniel, Katz, Ori, Shmul, Amir, Baum, Avi, Engelberg, Nir, Kaminitz, Guy, Danon, Or, Seznayov, Roi
Format: Patent
Sprache:eng
Schlagworte:
Online-Zugang:Volltext bestellen
Tags: Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
container_end_page
container_issue
container_start_page
container_title
container_volume
creator Adelstein, Yuval
Chibotero, Daniel
Katz, Ori
Shmul, Amir
Baum, Avi
Engelberg, Nir
Kaminitz, Guy
Danon, Or
Seznayov, Roi
description Novel and useful system and methods of several functional safety mechanisms for use in an artificial neural network (ANN) processor. The mechanisms can be deployed individually or in combination to provide a desired level of safety in neural networks. Multiple strategies are applied involving redundancy by design, redundancy through spatial mapping as well as self-tuning procedures that modify static (weights) and monitor dynamic (activations) behavior. The various mechanisms of the present invention address ANN system level safety in situ, as a system level strategy that is tightly coupled with the processor architecture. The NN processor incorporates several functional safety concepts which reduce its risk of failure that occurs during operation from going unnoticed. The mechanisms function to detect and promptly flag and report the occurrence of an error with some mechanisms capable of correction as well. The safety mechanisms cover data stream fault detection, software defined redundant allocation, cluster interlayer safety, cluster intralayer safety, layer control unit (LCU) instruction addressing, weights storage safety, and neural network intermediate results storage safety.
format Patent
fullrecord <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_US2022101043A1</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>US2022101043A1</sourcerecordid><originalsourceid>FETCH-epo_espacenet_US2022101043A13</originalsourceid><addsrcrecordid>eNrjZPB1ziktLkktUvDMKylKzEmsBDKDE9NSSyoVfFOTMxLzMotzgXIKjkBUVJKZlpmcmZij4JdaWgSmSsrzi7IVAoryk1OLi_OLeBhY0xJzilN5oTQ3g7Kba4izh25qQX58anFBYnJqXmpJfGiwkYGRkaGBoYGJsaOhMXGqAHVXNpM</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>Cluster Intralayer Safety Mechanism In An Artificial Neural Network Processor</title><source>esp@cenet</source><creator>Adelstein, Yuval ; Chibotero, Daniel ; Katz, Ori ; Shmul, Amir ; Baum, Avi ; Engelberg, Nir ; Kaminitz, Guy ; Danon, Or ; Seznayov, Roi</creator><creatorcontrib>Adelstein, Yuval ; Chibotero, Daniel ; Katz, Ori ; Shmul, Amir ; Baum, Avi ; Engelberg, Nir ; Kaminitz, Guy ; Danon, Or ; Seznayov, Roi</creatorcontrib><description>Novel and useful system and methods of several functional safety mechanisms for use in an artificial neural network (ANN) processor. The mechanisms can be deployed individually or in combination to provide a desired level of safety in neural networks. Multiple strategies are applied involving redundancy by design, redundancy through spatial mapping as well as self-tuning procedures that modify static (weights) and monitor dynamic (activations) behavior. The various mechanisms of the present invention address ANN system level safety in situ, as a system level strategy that is tightly coupled with the processor architecture. The NN processor incorporates several functional safety concepts which reduce its risk of failure that occurs during operation from going unnoticed. The mechanisms function to detect and promptly flag and report the occurrence of an error with some mechanisms capable of correction as well. The safety mechanisms cover data stream fault detection, software defined redundant allocation, cluster interlayer safety, cluster intralayer safety, layer control unit (LCU) instruction addressing, weights storage safety, and neural network intermediate results storage safety.</description><language>eng</language><subject>BASIC ELECTRONIC CIRCUITRY ; CALCULATING ; CODE CONVERSION IN GENERAL ; CODING ; COMPUTER SYSTEMS BASED ON SPECIFIC COMPUTATIONAL MODELS ; COMPUTING ; COUNTING ; DECODING ; ELECTRICITY ; HANDLING RECORD CARRIERS ; PHYSICS ; PRESENTATION OF DATA ; RECOGNITION OF DATA ; RECORD CARRIERS</subject><creationdate>2022</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=20220331&amp;DB=EPODOC&amp;CC=US&amp;NR=2022101043A1$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,776,881,25542,76516</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=20220331&amp;DB=EPODOC&amp;CC=US&amp;NR=2022101043A1$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>Adelstein, Yuval</creatorcontrib><creatorcontrib>Chibotero, Daniel</creatorcontrib><creatorcontrib>Katz, Ori</creatorcontrib><creatorcontrib>Shmul, Amir</creatorcontrib><creatorcontrib>Baum, Avi</creatorcontrib><creatorcontrib>Engelberg, Nir</creatorcontrib><creatorcontrib>Kaminitz, Guy</creatorcontrib><creatorcontrib>Danon, Or</creatorcontrib><creatorcontrib>Seznayov, Roi</creatorcontrib><title>Cluster Intralayer Safety Mechanism In An Artificial Neural Network Processor</title><description>Novel and useful system and methods of several functional safety mechanisms for use in an artificial neural network (ANN) processor. The mechanisms can be deployed individually or in combination to provide a desired level of safety in neural networks. Multiple strategies are applied involving redundancy by design, redundancy through spatial mapping as well as self-tuning procedures that modify static (weights) and monitor dynamic (activations) behavior. The various mechanisms of the present invention address ANN system level safety in situ, as a system level strategy that is tightly coupled with the processor architecture. The NN processor incorporates several functional safety concepts which reduce its risk of failure that occurs during operation from going unnoticed. The mechanisms function to detect and promptly flag and report the occurrence of an error with some mechanisms capable of correction as well. The safety mechanisms cover data stream fault detection, software defined redundant allocation, cluster interlayer safety, cluster intralayer safety, layer control unit (LCU) instruction addressing, weights storage safety, and neural network intermediate results storage safety.</description><subject>BASIC ELECTRONIC CIRCUITRY</subject><subject>CALCULATING</subject><subject>CODE CONVERSION IN GENERAL</subject><subject>CODING</subject><subject>COMPUTER SYSTEMS BASED ON SPECIFIC COMPUTATIONAL MODELS</subject><subject>COMPUTING</subject><subject>COUNTING</subject><subject>DECODING</subject><subject>ELECTRICITY</subject><subject>HANDLING RECORD CARRIERS</subject><subject>PHYSICS</subject><subject>PRESENTATION OF DATA</subject><subject>RECOGNITION OF DATA</subject><subject>RECORD CARRIERS</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2022</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZPB1ziktLkktUvDMKylKzEmsBDKDE9NSSyoVfFOTMxLzMotzgXIKjkBUVJKZlpmcmZij4JdaWgSmSsrzi7IVAoryk1OLi_OLeBhY0xJzilN5oTQ3g7Kba4izh25qQX58anFBYnJqXmpJfGiwkYGRkaGBoYGJsaOhMXGqAHVXNpM</recordid><startdate>20220331</startdate><enddate>20220331</enddate><creator>Adelstein, Yuval</creator><creator>Chibotero, Daniel</creator><creator>Katz, Ori</creator><creator>Shmul, Amir</creator><creator>Baum, Avi</creator><creator>Engelberg, Nir</creator><creator>Kaminitz, Guy</creator><creator>Danon, Or</creator><creator>Seznayov, Roi</creator><scope>EVB</scope></search><sort><creationdate>20220331</creationdate><title>Cluster Intralayer Safety Mechanism In An Artificial Neural Network Processor</title><author>Adelstein, Yuval ; Chibotero, Daniel ; Katz, Ori ; Shmul, Amir ; Baum, Avi ; Engelberg, Nir ; Kaminitz, Guy ; Danon, Or ; Seznayov, Roi</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_US2022101043A13</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>2022</creationdate><topic>BASIC ELECTRONIC CIRCUITRY</topic><topic>CALCULATING</topic><topic>CODE CONVERSION IN GENERAL</topic><topic>CODING</topic><topic>COMPUTER SYSTEMS BASED ON SPECIFIC COMPUTATIONAL MODELS</topic><topic>COMPUTING</topic><topic>COUNTING</topic><topic>DECODING</topic><topic>ELECTRICITY</topic><topic>HANDLING RECORD CARRIERS</topic><topic>PHYSICS</topic><topic>PRESENTATION OF DATA</topic><topic>RECOGNITION OF DATA</topic><topic>RECORD CARRIERS</topic><toplevel>online_resources</toplevel><creatorcontrib>Adelstein, Yuval</creatorcontrib><creatorcontrib>Chibotero, Daniel</creatorcontrib><creatorcontrib>Katz, Ori</creatorcontrib><creatorcontrib>Shmul, Amir</creatorcontrib><creatorcontrib>Baum, Avi</creatorcontrib><creatorcontrib>Engelberg, Nir</creatorcontrib><creatorcontrib>Kaminitz, Guy</creatorcontrib><creatorcontrib>Danon, Or</creatorcontrib><creatorcontrib>Seznayov, Roi</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Adelstein, Yuval</au><au>Chibotero, Daniel</au><au>Katz, Ori</au><au>Shmul, Amir</au><au>Baum, Avi</au><au>Engelberg, Nir</au><au>Kaminitz, Guy</au><au>Danon, Or</au><au>Seznayov, Roi</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>Cluster Intralayer Safety Mechanism In An Artificial Neural Network Processor</title><date>2022-03-31</date><risdate>2022</risdate><abstract>Novel and useful system and methods of several functional safety mechanisms for use in an artificial neural network (ANN) processor. The mechanisms can be deployed individually or in combination to provide a desired level of safety in neural networks. Multiple strategies are applied involving redundancy by design, redundancy through spatial mapping as well as self-tuning procedures that modify static (weights) and monitor dynamic (activations) behavior. The various mechanisms of the present invention address ANN system level safety in situ, as a system level strategy that is tightly coupled with the processor architecture. The NN processor incorporates several functional safety concepts which reduce its risk of failure that occurs during operation from going unnoticed. The mechanisms function to detect and promptly flag and report the occurrence of an error with some mechanisms capable of correction as well. The safety mechanisms cover data stream fault detection, software defined redundant allocation, cluster interlayer safety, cluster intralayer safety, layer control unit (LCU) instruction addressing, weights storage safety, and neural network intermediate results storage safety.</abstract><oa>free_for_read</oa></addata></record>
fulltext fulltext_linktorsrc
identifier
ispartof
issn
language eng
recordid cdi_epo_espacenet_US2022101043A1
source esp@cenet
subjects BASIC ELECTRONIC CIRCUITRY
CALCULATING
CODE CONVERSION IN GENERAL
CODING
COMPUTER SYSTEMS BASED ON SPECIFIC COMPUTATIONAL MODELS
COMPUTING
COUNTING
DECODING
ELECTRICITY
HANDLING RECORD CARRIERS
PHYSICS
PRESENTATION OF DATA
RECOGNITION OF DATA
RECORD CARRIERS
title Cluster Intralayer Safety Mechanism In An Artificial Neural Network Processor
url https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-02-19T02%3A55%3A50IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-epo_EVB&rft_val_fmt=info:ofi/fmt:kev:mtx:patent&rft.genre=patent&rft.au=Adelstein,%20Yuval&rft.date=2022-03-31&rft_id=info:doi/&rft_dat=%3Cepo_EVB%3EUS2022101043A1%3C/epo_EVB%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rfr_iscdi=true