FABRICATION OF GATE-ALL-AROUND INTEGRATED CIRCUIT STRUCTURES HAVING COMMON METAL GATES AND HAVING GATE DIELECTRICS WITH A DIPOLE LAYER

Gate-all-around integrated circuit structures having common metal gates and having gate dielectrics with a dipole layer are described. For example, an integrated circuit structure includes a first vertical arrangement of horizontal nanowires, and a second vertical arrangement of horizontal nanowires...

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Hauptverfasser: Crum, Dax M, Golonzka, Oleg, Ghani, Tahir, Lavric, Dan S
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creator Crum, Dax M
Golonzka, Oleg
Ghani, Tahir
Lavric, Dan S
description Gate-all-around integrated circuit structures having common metal gates and having gate dielectrics with a dipole layer are described. For example, an integrated circuit structure includes a first vertical arrangement of horizontal nanowires, and a second vertical arrangement of horizontal nanowires. A first gate stack is over the first vertical arrangement of horizontal nanowires, the first gate stack a PMOS gate stack having a P-type conductive layer on a first gate dielectric including a high-k dielectric layer on a first dipole material layer. A second gate stack is over the second vertical arrangement of horizontal nanowires, the second gate stack an NMOS gate stack having the P-type conductive layer on a second gate dielectric including the high-k dielectric layer on a second dipole material layer.
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fullrecord <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_US2022093596A1</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>US2022093596A1</sourcerecordid><originalsourceid>FETCH-epo_espacenet_US2022093596A13</originalsourceid><addsrcrecordid>eNqNjU0KwjAQhbtxIeodBlwXakWhyzGdtoE0kWSiuCpF4kq0UM_guY3SA7h68L2_efKu8GClQJZGg6mgRqYUlUrRGq9LkJqpthGWIKQVXjI4tl6wt-SgwZPUNQjTtrHeEqP6LTjA2J3cL4BSkiLB8crBWXIDGNHRKAKFF7LLZHbr72NYTbpI1hWxaNIwPLswDv01PMKr8y7P8jwrtrtij5vtf6kPr14-fw</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>FABRICATION OF GATE-ALL-AROUND INTEGRATED CIRCUIT STRUCTURES HAVING COMMON METAL GATES AND HAVING GATE DIELECTRICS WITH A DIPOLE LAYER</title><source>esp@cenet</source><creator>Crum, Dax M ; Golonzka, Oleg ; Ghani, Tahir ; Lavric, Dan S</creator><creatorcontrib>Crum, Dax M ; Golonzka, Oleg ; Ghani, Tahir ; Lavric, Dan S</creatorcontrib><description>Gate-all-around integrated circuit structures having common metal gates and having gate dielectrics with a dipole layer are described. For example, an integrated circuit structure includes a first vertical arrangement of horizontal nanowires, and a second vertical arrangement of horizontal nanowires. A first gate stack is over the first vertical arrangement of horizontal nanowires, the first gate stack a PMOS gate stack having a P-type conductive layer on a first gate dielectric including a high-k dielectric layer on a first dipole material layer. A second gate stack is over the second vertical arrangement of horizontal nanowires, the second gate stack an NMOS gate stack having the P-type conductive layer on a second gate dielectric including the high-k dielectric layer on a second dipole material layer.</description><language>eng</language><subject>BASIC ELECTRIC ELEMENTS ; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ; ELECTRICITY ; SEMICONDUCTOR DEVICES</subject><creationdate>2022</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=20220324&amp;DB=EPODOC&amp;CC=US&amp;NR=2022093596A1$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,780,885,25563,76318</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=20220324&amp;DB=EPODOC&amp;CC=US&amp;NR=2022093596A1$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>Crum, Dax M</creatorcontrib><creatorcontrib>Golonzka, Oleg</creatorcontrib><creatorcontrib>Ghani, Tahir</creatorcontrib><creatorcontrib>Lavric, Dan S</creatorcontrib><title>FABRICATION OF GATE-ALL-AROUND INTEGRATED CIRCUIT STRUCTURES HAVING COMMON METAL GATES AND HAVING GATE DIELECTRICS WITH A DIPOLE LAYER</title><description>Gate-all-around integrated circuit structures having common metal gates and having gate dielectrics with a dipole layer are described. For example, an integrated circuit structure includes a first vertical arrangement of horizontal nanowires, and a second vertical arrangement of horizontal nanowires. A first gate stack is over the first vertical arrangement of horizontal nanowires, the first gate stack a PMOS gate stack having a P-type conductive layer on a first gate dielectric including a high-k dielectric layer on a first dipole material layer. A second gate stack is over the second vertical arrangement of horizontal nanowires, the second gate stack an NMOS gate stack having the P-type conductive layer on a second gate dielectric including the high-k dielectric layer on a second dipole material layer.</description><subject>BASIC ELECTRIC ELEMENTS</subject><subject>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</subject><subject>ELECTRICITY</subject><subject>SEMICONDUCTOR DEVICES</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2022</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNqNjU0KwjAQhbtxIeodBlwXakWhyzGdtoE0kWSiuCpF4kq0UM_guY3SA7h68L2_efKu8GClQJZGg6mgRqYUlUrRGq9LkJqpthGWIKQVXjI4tl6wt-SgwZPUNQjTtrHeEqP6LTjA2J3cL4BSkiLB8crBWXIDGNHRKAKFF7LLZHbr72NYTbpI1hWxaNIwPLswDv01PMKr8y7P8jwrtrtij5vtf6kPr14-fw</recordid><startdate>20220324</startdate><enddate>20220324</enddate><creator>Crum, Dax M</creator><creator>Golonzka, Oleg</creator><creator>Ghani, Tahir</creator><creator>Lavric, Dan S</creator><scope>EVB</scope></search><sort><creationdate>20220324</creationdate><title>FABRICATION OF GATE-ALL-AROUND INTEGRATED CIRCUIT STRUCTURES HAVING COMMON METAL GATES AND HAVING GATE DIELECTRICS WITH A DIPOLE LAYER</title><author>Crum, Dax M ; Golonzka, Oleg ; Ghani, Tahir ; Lavric, Dan S</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_US2022093596A13</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>2022</creationdate><topic>BASIC ELECTRIC ELEMENTS</topic><topic>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</topic><topic>ELECTRICITY</topic><topic>SEMICONDUCTOR DEVICES</topic><toplevel>online_resources</toplevel><creatorcontrib>Crum, Dax M</creatorcontrib><creatorcontrib>Golonzka, Oleg</creatorcontrib><creatorcontrib>Ghani, Tahir</creatorcontrib><creatorcontrib>Lavric, Dan S</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Crum, Dax M</au><au>Golonzka, Oleg</au><au>Ghani, Tahir</au><au>Lavric, Dan S</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>FABRICATION OF GATE-ALL-AROUND INTEGRATED CIRCUIT STRUCTURES HAVING COMMON METAL GATES AND HAVING GATE DIELECTRICS WITH A DIPOLE LAYER</title><date>2022-03-24</date><risdate>2022</risdate><abstract>Gate-all-around integrated circuit structures having common metal gates and having gate dielectrics with a dipole layer are described. For example, an integrated circuit structure includes a first vertical arrangement of horizontal nanowires, and a second vertical arrangement of horizontal nanowires. A first gate stack is over the first vertical arrangement of horizontal nanowires, the first gate stack a PMOS gate stack having a P-type conductive layer on a first gate dielectric including a high-k dielectric layer on a first dipole material layer. A second gate stack is over the second vertical arrangement of horizontal nanowires, the second gate stack an NMOS gate stack having the P-type conductive layer on a second gate dielectric including the high-k dielectric layer on a second dipole material layer.</abstract><oa>free_for_read</oa></addata></record>
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subjects BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
SEMICONDUCTOR DEVICES
title FABRICATION OF GATE-ALL-AROUND INTEGRATED CIRCUIT STRUCTURES HAVING COMMON METAL GATES AND HAVING GATE DIELECTRICS WITH A DIPOLE LAYER
url https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-01-11T22%3A58%3A27IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-epo_EVB&rft_val_fmt=info:ofi/fmt:kev:mtx:patent&rft.genre=patent&rft.au=Crum,%20Dax%20M&rft.date=2022-03-24&rft_id=info:doi/&rft_dat=%3Cepo_EVB%3EUS2022093596A1%3C/epo_EVB%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rfr_iscdi=true