System on a Chip that Drives Display when CPUs are Powered Down
In an embodiment, a system may include one or more processors forming central processing units (CPUs) in the system, a display controller configured to display frames on a display device, a memory controller configured to control a memory, and a power management circuit. The power management circuit...
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| creator | Holland, Peter F Rachakonda, Ramana V Gupta, Rohit K Simeral, Brad W |
| description | In an embodiment, a system may include one or more processors forming central processing units (CPUs) in the system, a display controller configured to display frames on a display device, a memory controller configured to control a memory, and a power management circuit. The power management circuit may be configured to establish one of a plurality of power states in the system. In a first power state, the display controller and the memory controller are powered on while the CPUs are powered off. The display controller may be configured to read a plurality of prerendered frames from the memory and display the plurality of prerendered frames at times specified for each of the plurality of prerendered frames. |
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The power management circuit may be configured to establish one of a plurality of power states in the system. In a first power state, the display controller and the memory controller are powered on while the CPUs are powered off. The display controller may be configured to read a plurality of prerendered frames from the memory and display the plurality of prerendered frames at times specified for each of the plurality of prerendered frames.</description><language>eng</language><subject>CALCULATING ; COMPUTING ; COUNTING ; ELECTRIC DIGITAL DATA PROCESSING ; PHYSICS</subject><creationdate>2022</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20220310&DB=EPODOC&CC=US&NR=2022075440A1$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,780,885,25564,76547</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20220310&DB=EPODOC&CC=US&NR=2022075440A1$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>Holland, Peter F</creatorcontrib><creatorcontrib>Rachakonda, Ramana V</creatorcontrib><creatorcontrib>Gupta, Rohit K</creatorcontrib><creatorcontrib>Simeral, Brad W</creatorcontrib><title>System on a Chip that Drives Display when CPUs are Powered Down</title><description>In an embodiment, a system may include one or more processors forming central processing units (CPUs) in the system, a display controller configured to display frames on a display device, a memory controller configured to control a memory, and a power management circuit. The power management circuit may be configured to establish one of a plurality of power states in the system. In a first power state, the display controller and the memory controller are powered on while the CPUs are powered off. The display controller may be configured to read a plurality of prerendered frames from the memory and display the plurality of prerendered frames at times specified for each of the plurality of prerendered frames.</description><subject>CALCULATING</subject><subject>COMPUTING</subject><subject>COUNTING</subject><subject>ELECTRIC DIGITAL DATA PROCESSING</subject><subject>PHYSICS</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2022</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZLAPriwuSc1VyM9TSFRwzsgsUCjJSCxRcCnKLEstVnDJLC7ISaxUKM9IzVNwDggtVkgsSlUIyC9PLUpNUXDJL8_jYWBNS8wpTuWF0twMym6uIc4euqkF-fGpxQWJyal5qSXxocFGBkZGBuamJiYGjobGxKkCAKApMFw</recordid><startdate>20220310</startdate><enddate>20220310</enddate><creator>Holland, Peter F</creator><creator>Rachakonda, Ramana V</creator><creator>Gupta, Rohit K</creator><creator>Simeral, Brad W</creator><scope>EVB</scope></search><sort><creationdate>20220310</creationdate><title>System on a Chip that Drives Display when CPUs are Powered Down</title><author>Holland, Peter F ; Rachakonda, Ramana V ; Gupta, Rohit K ; Simeral, Brad W</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_US2022075440A13</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>2022</creationdate><topic>CALCULATING</topic><topic>COMPUTING</topic><topic>COUNTING</topic><topic>ELECTRIC DIGITAL DATA PROCESSING</topic><topic>PHYSICS</topic><toplevel>online_resources</toplevel><creatorcontrib>Holland, Peter F</creatorcontrib><creatorcontrib>Rachakonda, Ramana V</creatorcontrib><creatorcontrib>Gupta, Rohit K</creatorcontrib><creatorcontrib>Simeral, Brad W</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Holland, Peter F</au><au>Rachakonda, Ramana V</au><au>Gupta, Rohit K</au><au>Simeral, Brad W</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>System on a Chip that Drives Display when CPUs are Powered Down</title><date>2022-03-10</date><risdate>2022</risdate><abstract>In an embodiment, a system may include one or more processors forming central processing units (CPUs) in the system, a display controller configured to display frames on a display device, a memory controller configured to control a memory, and a power management circuit. The power management circuit may be configured to establish one of a plurality of power states in the system. In a first power state, the display controller and the memory controller are powered on while the CPUs are powered off. The display controller may be configured to read a plurality of prerendered frames from the memory and display the plurality of prerendered frames at times specified for each of the plurality of prerendered frames.</abstract><oa>free_for_read</oa></addata></record> |
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| subjects | CALCULATING COMPUTING COUNTING ELECTRIC DIGITAL DATA PROCESSING PHYSICS |
| title | System on a Chip that Drives Display when CPUs are Powered Down |
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