APPARATUS AND METHODS FOR SYNCHRONIZING A PLURALITY OF DOUBLE DATA RATE MEMORY RANKS

A shared data transfer clock is used among double data rate memory ranks. A memory controller processes incoming memory access commands destined for at least one of a plurality of double data rate memory ranks and determines when a target DDR memory rank is out of synchronization with respect to the...

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Bibliographische Detailangaben

1. Verfasser:	Askar, Tahsin
Format:	Patent
Sprache:	eng
Schlagworte:	CALCULATING COMPUTING COUNTING ELECTRIC DIGITAL DATA PROCESSING PHYSICS
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