DISPLAY DEVICE
A display device comprises a base substrate, a lower interlayer dielectric layer, an oxide semiconductor layer including a first channel region, a first drain region disposed on one side of the first channel region, and a first source region, a first gate insulating layer, a first upper gate electro...
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| creator | SEO, Ki Seong YOON, Hee Won SEO, Jung Yub TANAKA, Tetsuhiro KIM, Yeong Gyu |
| description | A display device comprises a base substrate, a lower interlayer dielectric layer, an oxide semiconductor layer including a first channel region, a first drain region disposed on one side of the first channel region, and a first source region, a first gate insulating layer, a first upper gate electrode, an upper interlayer dielectric layer, and a first source electrode and a first drain electrode, wherein the lower interlayer dielectric layer includes a first lower interlayer dielectric layer disposed on the base substrate, and a second lower interlayer dielectric layer disposed on the first lower interlayer dielectric layer, wherein the first lower interlayer dielectric layer includes silicon nitride and the second lower interlayer dielectric layer comprises silicon oxide, and wherein a composition ratio of nitrogen to silicon in the first lower interlayer dielectric layer ranges from 0.8 to 0.89. |
| format | Patent |
| fullrecord | <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_US2022005901A1</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>US2022005901A1</sourcerecordid><originalsourceid>FETCH-epo_espacenet_US2022005901A13</originalsourceid><addsrcrecordid>eNrjZOBz8QwO8HGMVHBxDfN0duVhYE1LzClO5YXS3AzKbq4hzh66qQX58anFBYnJqXmpJfGhwUYGRkYGBqaWBoaOhsbEqQIANCcduQ</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>DISPLAY DEVICE</title><source>esp@cenet</source><creator>SEO, Ki Seong ; YOON, Hee Won ; SEO, Jung Yub ; TANAKA, Tetsuhiro ; KIM, Yeong Gyu</creator><creatorcontrib>SEO, Ki Seong ; YOON, Hee Won ; SEO, Jung Yub ; TANAKA, Tetsuhiro ; KIM, Yeong Gyu</creatorcontrib><description>A display device comprises a base substrate, a lower interlayer dielectric layer, an oxide semiconductor layer including a first channel region, a first drain region disposed on one side of the first channel region, and a first source region, a first gate insulating layer, a first upper gate electrode, an upper interlayer dielectric layer, and a first source electrode and a first drain electrode, wherein the lower interlayer dielectric layer includes a first lower interlayer dielectric layer disposed on the base substrate, and a second lower interlayer dielectric layer disposed on the first lower interlayer dielectric layer, wherein the first lower interlayer dielectric layer includes silicon nitride and the second lower interlayer dielectric layer comprises silicon oxide, and wherein a composition ratio of nitrogen to silicon in the first lower interlayer dielectric layer ranges from 0.8 to 0.89.</description><language>eng</language><subject>BASIC ELECTRIC ELEMENTS ; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ; ELECTRICITY ; SEMICONDUCTOR DEVICES</subject><creationdate>2022</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20220106&DB=EPODOC&CC=US&NR=2022005901A1$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,780,885,25564,76547</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20220106&DB=EPODOC&CC=US&NR=2022005901A1$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>SEO, Ki Seong</creatorcontrib><creatorcontrib>YOON, Hee Won</creatorcontrib><creatorcontrib>SEO, Jung Yub</creatorcontrib><creatorcontrib>TANAKA, Tetsuhiro</creatorcontrib><creatorcontrib>KIM, Yeong Gyu</creatorcontrib><title>DISPLAY DEVICE</title><description>A display device comprises a base substrate, a lower interlayer dielectric layer, an oxide semiconductor layer including a first channel region, a first drain region disposed on one side of the first channel region, and a first source region, a first gate insulating layer, a first upper gate electrode, an upper interlayer dielectric layer, and a first source electrode and a first drain electrode, wherein the lower interlayer dielectric layer includes a first lower interlayer dielectric layer disposed on the base substrate, and a second lower interlayer dielectric layer disposed on the first lower interlayer dielectric layer, wherein the first lower interlayer dielectric layer includes silicon nitride and the second lower interlayer dielectric layer comprises silicon oxide, and wherein a composition ratio of nitrogen to silicon in the first lower interlayer dielectric layer ranges from 0.8 to 0.89.</description><subject>BASIC ELECTRIC ELEMENTS</subject><subject>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</subject><subject>ELECTRICITY</subject><subject>SEMICONDUCTOR DEVICES</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2022</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZOBz8QwO8HGMVHBxDfN0duVhYE1LzClO5YXS3AzKbq4hzh66qQX58anFBYnJqXmpJfGhwUYGRkYGBqaWBoaOhsbEqQIANCcduQ</recordid><startdate>20220106</startdate><enddate>20220106</enddate><creator>SEO, Ki Seong</creator><creator>YOON, Hee Won</creator><creator>SEO, Jung Yub</creator><creator>TANAKA, Tetsuhiro</creator><creator>KIM, Yeong Gyu</creator><scope>EVB</scope></search><sort><creationdate>20220106</creationdate><title>DISPLAY DEVICE</title><author>SEO, Ki Seong ; YOON, Hee Won ; SEO, Jung Yub ; TANAKA, Tetsuhiro ; KIM, Yeong Gyu</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_US2022005901A13</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>2022</creationdate><topic>BASIC ELECTRIC ELEMENTS</topic><topic>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</topic><topic>ELECTRICITY</topic><topic>SEMICONDUCTOR DEVICES</topic><toplevel>online_resources</toplevel><creatorcontrib>SEO, Ki Seong</creatorcontrib><creatorcontrib>YOON, Hee Won</creatorcontrib><creatorcontrib>SEO, Jung Yub</creatorcontrib><creatorcontrib>TANAKA, Tetsuhiro</creatorcontrib><creatorcontrib>KIM, Yeong Gyu</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>SEO, Ki Seong</au><au>YOON, Hee Won</au><au>SEO, Jung Yub</au><au>TANAKA, Tetsuhiro</au><au>KIM, Yeong Gyu</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>DISPLAY DEVICE</title><date>2022-01-06</date><risdate>2022</risdate><abstract>A display device comprises a base substrate, a lower interlayer dielectric layer, an oxide semiconductor layer including a first channel region, a first drain region disposed on one side of the first channel region, and a first source region, a first gate insulating layer, a first upper gate electrode, an upper interlayer dielectric layer, and a first source electrode and a first drain electrode, wherein the lower interlayer dielectric layer includes a first lower interlayer dielectric layer disposed on the base substrate, and a second lower interlayer dielectric layer disposed on the first lower interlayer dielectric layer, wherein the first lower interlayer dielectric layer includes silicon nitride and the second lower interlayer dielectric layer comprises silicon oxide, and wherein a composition ratio of nitrogen to silicon in the first lower interlayer dielectric layer ranges from 0.8 to 0.89.</abstract><oa>free_for_read</oa></addata></record> |
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| subjects | BASIC ELECTRIC ELEMENTS ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ELECTRICITY SEMICONDUCTOR DEVICES |
| title | DISPLAY DEVICE |
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