METAL OXIDE SEMICONDUCTOR INTEGRATED CIRCUIT BASIC UNIT
A MOS integrated circuit basic unit includes: a drain semiconductor region; a lightly doped drain region; a channel semiconductor region; a source semiconductor region; a source electrode; a gate electrode; a gate dielectric layer; and a drain electrode. The drain semiconductor region is the bottom...
Gespeichert in:
Hauptverfasser: | , , , , , , , , , , |
---|---|
Format: | Patent |
Sprache: | eng |
Schlagworte: | |
Online-Zugang: | Volltext bestellen |
Tags: |
Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
|
container_end_page | |
---|---|
container_issue | |
container_start_page | |
container_title | |
container_volume | |
creator | FENG, Ke TANG, Ruifeng LIAO, Yongbo NIE, Ruihong ZENG, Xianghe LI, Ping HU, Zhaoxi LIN, Fan PENG, Chenxi LI, Yaosen ZOU, Jiarui |
description | A MOS integrated circuit basic unit includes: a drain semiconductor region; a lightly doped drain region; a channel semiconductor region; a source semiconductor region; a source electrode; a gate electrode; a gate dielectric layer; and a drain electrode. The drain semiconductor region is the bottom of the basic unit. The gate electrode has a ring structure, which surrounds the channel semiconductor region, the source semiconductor region and the lightly doped drain region. The upper surface of the gate electrode is aligned to the upper surface of the source semiconductor region; and a bottom surface of the gate electrode is lower than an interface of the lightly doped drain region and the drain semiconductor region. The gate dielectric layer is disposed between the gate electrode and the adjacent functional layer. The drain semiconductor region is connected to the drain electrode of the basic unit. |
format | Patent |
fullrecord | <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_US2021226022A1</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>US2021226022A1</sourcerecordid><originalsourceid>FETCH-epo_espacenet_US2021226022A13</originalsourceid><addsrcrecordid>eNrjZDD3dQ1x9FHwj_B0cVUIdvX1dPb3cwl1DvEPUvD0C3F1D3IMcXVRcPYMcg71DFFwcgz2dFYI9fMM4WFgTUvMKU7lhdLcDMpuriHOHrqpBfnxqcUFicmpeakl8aHBRgZGhkZGZgZGRo6GxsSpAgDmxikf</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>METAL OXIDE SEMICONDUCTOR INTEGRATED CIRCUIT BASIC UNIT</title><source>esp@cenet</source><creator>FENG, Ke ; TANG, Ruifeng ; LIAO, Yongbo ; NIE, Ruihong ; ZENG, Xianghe ; LI, Ping ; HU, Zhaoxi ; LIN, Fan ; PENG, Chenxi ; LI, Yaosen ; ZOU, Jiarui</creator><creatorcontrib>FENG, Ke ; TANG, Ruifeng ; LIAO, Yongbo ; NIE, Ruihong ; ZENG, Xianghe ; LI, Ping ; HU, Zhaoxi ; LIN, Fan ; PENG, Chenxi ; LI, Yaosen ; ZOU, Jiarui</creatorcontrib><description>A MOS integrated circuit basic unit includes: a drain semiconductor region; a lightly doped drain region; a channel semiconductor region; a source semiconductor region; a source electrode; a gate electrode; a gate dielectric layer; and a drain electrode. The drain semiconductor region is the bottom of the basic unit. The gate electrode has a ring structure, which surrounds the channel semiconductor region, the source semiconductor region and the lightly doped drain region. The upper surface of the gate electrode is aligned to the upper surface of the source semiconductor region; and a bottom surface of the gate electrode is lower than an interface of the lightly doped drain region and the drain semiconductor region. The gate dielectric layer is disposed between the gate electrode and the adjacent functional layer. The drain semiconductor region is connected to the drain electrode of the basic unit.</description><language>eng</language><subject>APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC,OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWERSUPPLY SYSTEMS ; BASIC ELECTRIC ELEMENTS ; CONTROL OR REGULATION THEREOF ; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUTPOWER ; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER ; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ; ELECTRICITY ; GENERATION ; SEMICONDUCTOR DEVICES</subject><creationdate>2021</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20210722&DB=EPODOC&CC=US&NR=2021226022A1$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,776,881,25544,76293</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20210722&DB=EPODOC&CC=US&NR=2021226022A1$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>FENG, Ke</creatorcontrib><creatorcontrib>TANG, Ruifeng</creatorcontrib><creatorcontrib>LIAO, Yongbo</creatorcontrib><creatorcontrib>NIE, Ruihong</creatorcontrib><creatorcontrib>ZENG, Xianghe</creatorcontrib><creatorcontrib>LI, Ping</creatorcontrib><creatorcontrib>HU, Zhaoxi</creatorcontrib><creatorcontrib>LIN, Fan</creatorcontrib><creatorcontrib>PENG, Chenxi</creatorcontrib><creatorcontrib>LI, Yaosen</creatorcontrib><creatorcontrib>ZOU, Jiarui</creatorcontrib><title>METAL OXIDE SEMICONDUCTOR INTEGRATED CIRCUIT BASIC UNIT</title><description>A MOS integrated circuit basic unit includes: a drain semiconductor region; a lightly doped drain region; a channel semiconductor region; a source semiconductor region; a source electrode; a gate electrode; a gate dielectric layer; and a drain electrode. The drain semiconductor region is the bottom of the basic unit. The gate electrode has a ring structure, which surrounds the channel semiconductor region, the source semiconductor region and the lightly doped drain region. The upper surface of the gate electrode is aligned to the upper surface of the source semiconductor region; and a bottom surface of the gate electrode is lower than an interface of the lightly doped drain region and the drain semiconductor region. The gate dielectric layer is disposed between the gate electrode and the adjacent functional layer. The drain semiconductor region is connected to the drain electrode of the basic unit.</description><subject>APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC,OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWERSUPPLY SYSTEMS</subject><subject>BASIC ELECTRIC ELEMENTS</subject><subject>CONTROL OR REGULATION THEREOF</subject><subject>CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUTPOWER</subject><subject>CONVERSION OR DISTRIBUTION OF ELECTRIC POWER</subject><subject>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</subject><subject>ELECTRICITY</subject><subject>GENERATION</subject><subject>SEMICONDUCTOR DEVICES</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2021</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZDD3dQ1x9FHwj_B0cVUIdvX1dPb3cwl1DvEPUvD0C3F1D3IMcXVRcPYMcg71DFFwcgz2dFYI9fMM4WFgTUvMKU7lhdLcDMpuriHOHrqpBfnxqcUFicmpeakl8aHBRgZGhkZGZgZGRo6GxsSpAgDmxikf</recordid><startdate>20210722</startdate><enddate>20210722</enddate><creator>FENG, Ke</creator><creator>TANG, Ruifeng</creator><creator>LIAO, Yongbo</creator><creator>NIE, Ruihong</creator><creator>ZENG, Xianghe</creator><creator>LI, Ping</creator><creator>HU, Zhaoxi</creator><creator>LIN, Fan</creator><creator>PENG, Chenxi</creator><creator>LI, Yaosen</creator><creator>ZOU, Jiarui</creator><scope>EVB</scope></search><sort><creationdate>20210722</creationdate><title>METAL OXIDE SEMICONDUCTOR INTEGRATED CIRCUIT BASIC UNIT</title><author>FENG, Ke ; TANG, Ruifeng ; LIAO, Yongbo ; NIE, Ruihong ; ZENG, Xianghe ; LI, Ping ; HU, Zhaoxi ; LIN, Fan ; PENG, Chenxi ; LI, Yaosen ; ZOU, Jiarui</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_US2021226022A13</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>2021</creationdate><topic>APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC,OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWERSUPPLY SYSTEMS</topic><topic>BASIC ELECTRIC ELEMENTS</topic><topic>CONTROL OR REGULATION THEREOF</topic><topic>CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUTPOWER</topic><topic>CONVERSION OR DISTRIBUTION OF ELECTRIC POWER</topic><topic>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</topic><topic>ELECTRICITY</topic><topic>GENERATION</topic><topic>SEMICONDUCTOR DEVICES</topic><toplevel>online_resources</toplevel><creatorcontrib>FENG, Ke</creatorcontrib><creatorcontrib>TANG, Ruifeng</creatorcontrib><creatorcontrib>LIAO, Yongbo</creatorcontrib><creatorcontrib>NIE, Ruihong</creatorcontrib><creatorcontrib>ZENG, Xianghe</creatorcontrib><creatorcontrib>LI, Ping</creatorcontrib><creatorcontrib>HU, Zhaoxi</creatorcontrib><creatorcontrib>LIN, Fan</creatorcontrib><creatorcontrib>PENG, Chenxi</creatorcontrib><creatorcontrib>LI, Yaosen</creatorcontrib><creatorcontrib>ZOU, Jiarui</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>FENG, Ke</au><au>TANG, Ruifeng</au><au>LIAO, Yongbo</au><au>NIE, Ruihong</au><au>ZENG, Xianghe</au><au>LI, Ping</au><au>HU, Zhaoxi</au><au>LIN, Fan</au><au>PENG, Chenxi</au><au>LI, Yaosen</au><au>ZOU, Jiarui</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>METAL OXIDE SEMICONDUCTOR INTEGRATED CIRCUIT BASIC UNIT</title><date>2021-07-22</date><risdate>2021</risdate><abstract>A MOS integrated circuit basic unit includes: a drain semiconductor region; a lightly doped drain region; a channel semiconductor region; a source semiconductor region; a source electrode; a gate electrode; a gate dielectric layer; and a drain electrode. The drain semiconductor region is the bottom of the basic unit. The gate electrode has a ring structure, which surrounds the channel semiconductor region, the source semiconductor region and the lightly doped drain region. The upper surface of the gate electrode is aligned to the upper surface of the source semiconductor region; and a bottom surface of the gate electrode is lower than an interface of the lightly doped drain region and the drain semiconductor region. The gate dielectric layer is disposed between the gate electrode and the adjacent functional layer. The drain semiconductor region is connected to the drain electrode of the basic unit.</abstract><oa>free_for_read</oa></addata></record> |
fulltext | fulltext_linktorsrc |
identifier | |
ispartof | |
issn | |
language | eng |
recordid | cdi_epo_espacenet_US2021226022A1 |
source | esp@cenet |
subjects | APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC,OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWERSUPPLY SYSTEMS BASIC ELECTRIC ELEMENTS CONTROL OR REGULATION THEREOF CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUTPOWER CONVERSION OR DISTRIBUTION OF ELECTRIC POWER ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ELECTRICITY GENERATION SEMICONDUCTOR DEVICES |
title | METAL OXIDE SEMICONDUCTOR INTEGRATED CIRCUIT BASIC UNIT |
url | https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-01-27T20%3A18%3A18IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-epo_EVB&rft_val_fmt=info:ofi/fmt:kev:mtx:patent&rft.genre=patent&rft.au=FENG,%20Ke&rft.date=2021-07-22&rft_id=info:doi/&rft_dat=%3Cepo_EVB%3EUS2021226022A1%3C/epo_EVB%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rfr_iscdi=true |