SEQUENTIAL ERROR CAPTURE DURING MEMORY TEST

Embodiments of the present invention are directed to methods, systems, and circuitry for memory arrays. A system for testing a memory array having self-test circuitry includes a register having register latches operable to receive error logic signals having respective first states or second states....

Ausführliche Beschreibung

Bibliographische Detailangaben

Hauptverfasser:	Rodko, Daniel, Patel, Pradip, Huott, William
Format:	Patent
Sprache:	eng
Schlagworte:	INFORMATION STORAGE PHYSICS STATIC STORES
Online-Zugang:	Volltext bestellen
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