STRESS LAYOUT OPTIMIZATION FOR DEVICE PERFORMANCE

STRESS LAYOUT OPTIMIZATION FOR DEVICE PERFORMANCE

The present disclosure relates to semiconductor structures and, more particularly, to a layout optimization for radio frequency (RF) device performance and methods of manufacture. The structure includes: a first active device on a substrate; source and drain diffusion regions adjacent to the first a...

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Hauptverfasser: UTESS, Dirk, SAADAT, Irfan A, KLEIMAIER, Dominik M, ZHAO, Zhixing, RAVAUX, Florent
Format: Patent
Sprache:eng
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BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
SEMICONDUCTOR DEVICES
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creator UTESS, Dirk
SAADAT, Irfan A
KLEIMAIER, Dominik M
ZHAO, Zhixing
RAVAUX, Florent
description The present disclosure relates to semiconductor structures and, more particularly, to a layout optimization for radio frequency (RF) device performance and methods of manufacture. The structure includes: a first active device on a substrate; source and drain diffusion regions adjacent to the first active device; and a first contact in electrical contact with the source and drain diffusion regions and which is spaced away from the first active device to optimize a stress component in a channel region of the first active device.
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subjects BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
SEMICONDUCTOR DEVICES
title STRESS LAYOUT OPTIMIZATION FOR DEVICE PERFORMANCE
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