ENHANCEMENT MODE III-NITRIDE DEVICES HAVING AN AL1-XSIXO GATE INSULATOR
A transistor includes a III-N channel layer; a III-N barrier layer on the III-N channel layer; a source contact and a drain contact, the source and drain contacts electrically coupled to the III-N channel layer; an insulator layer on the III-N barrier layer; a gate insulator partially on the insulat...
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| creator | Liu, Xiang Kikkawa, Toshihide Rhodes, David Michael Mishra, Umesh Wu, Mo Gritters, John Kirk Lal, Rakesh K Neufeld, Carl Joseph |
| description | A transistor includes a III-N channel layer; a III-N barrier layer on the III-N channel layer; a source contact and a drain contact, the source and drain contacts electrically coupled to the III-N channel layer; an insulator layer on the III-N barrier layer; a gate insulator partially on the insulator layer and partially on the III-N channel layer, the gate insulator including an amorphous Al1-xSixO layer with 0.2 |
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Wu, Mo ; Gritters, John Kirk ; Lal, Rakesh K ; Neufeld, Carl Joseph</creatorcontrib><description>A transistor includes a III-N channel layer; a III-N barrier layer on the III-N channel layer; a source contact and a drain contact, the source and drain contacts electrically coupled to the III-N channel layer; an insulator layer on the III-N barrier layer; a gate insulator partially on the insulator layer and partially on the III-N channel layer, the gate insulator including an amorphous Al1-xSixO layer with 0.2<x<0.8; and a gate electrode over the gate insulator, the gate electrode being positioned between the source and drain contacts.</description><language>eng</language><subject>BASIC ELECTRIC ELEMENTS ; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ; ELECTRICITY ; SEMICONDUCTOR DEVICES</subject><creationdate>2021</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20210211&DB=EPODOC&CC=US&NR=2021043750A1$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,776,881,25542,76289</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20210211&DB=EPODOC&CC=US&NR=2021043750A1$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>Liu, Xiang</creatorcontrib><creatorcontrib>Kikkawa, Toshihide</creatorcontrib><creatorcontrib>Rhodes, David Michael</creatorcontrib><creatorcontrib>Mishra, Umesh</creatorcontrib><creatorcontrib>Wu, Mo</creatorcontrib><creatorcontrib>Gritters, John Kirk</creatorcontrib><creatorcontrib>Lal, Rakesh K</creatorcontrib><creatorcontrib>Neufeld, Carl Joseph</creatorcontrib><title>ENHANCEMENT MODE III-NITRIDE DEVICES HAVING AN AL1-XSIXO GATE INSULATOR</title><description>A transistor includes a III-N channel layer; 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a III-N barrier layer on the III-N channel layer; a source contact and a drain contact, the source and drain contacts electrically coupled to the III-N channel layer; an insulator layer on the III-N barrier layer; a gate insulator partially on the insulator layer and partially on the III-N channel layer, the gate insulator including an amorphous Al1-xSixO layer with 0.2<x<0.8; and a gate electrode over the gate insulator, the gate electrode being positioned between the source and drain contacts.</abstract><oa>free_for_read</oa></addata></record> |
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| subjects | BASIC ELECTRIC ELEMENTS ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ELECTRICITY SEMICONDUCTOR DEVICES |
| title | ENHANCEMENT MODE III-NITRIDE DEVICES HAVING AN AL1-XSIXO GATE INSULATOR |
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