MEMORY ARRAYS WITH VERTICAL TRANSISTORS AND THE FORMATION THEREOF

An apparatus, such as a memory array, can have a memory cell coupled to a first digit line (e.g., a local digit line) at a first level. A second digit line (e.g., hierarchical digit line) at a second level can be coupled to a main sense amplifier. A charge sharing device at a third level between the...

Ausführliche Beschreibung

Bibliographische Detailangaben

Hauptverfasser:	Simsek-Ege, Fatma Arzum, Robbs, Toby D, Cole, Steve V, Derner, Scott J
Format:	Patent
Sprache:	eng
Schlagworte:	BASIC ELECTRIC ELEMENTS ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ELECTRICITY INFORMATION STORAGE PHYSICS SEMICONDUCTOR DEVICES STATIC STORES
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