APPARATUS WITH REDUCED HARDWARE REGISTER SET USING REGISTER-EMULATING MEMORY LOCATION TO EMULATE ARCHITECTURAL REGISTER

An apparatus comprises processing circuitry for processing program instructions according to a predetermined architecture defining a number of architectural registers accessible in response to the program instructions. A set of hardware registers is provided in hardware. A storage capacity of the set of hardware registers is insufficient for storing all the data associated with the architectural registers of the pre-determined architecture. Control circuitry is responsive to the program instructions to transfer data between the hardware registers and at least one register-emulating memory location in memory for storing data corresponding to the architectural registers of the architecture.