METHOD AND STRUCTURE FOR FINFET DEVICES

A method for forming a semiconductor device comprises receiving a structure having a substrate, an isolation structure over the substrate, and a fin over the substrate and adjacent to the isolation structure. The method further includes etching a portion of the fin, resulting in a trench, forming a...

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Hauptverfasser: Chen, Hou-Yu, Lu, Yong-Yan, Soong, Chia-Wei
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Lu, Yong-Yan
Soong, Chia-Wei
description A method for forming a semiconductor device comprises receiving a structure having a substrate, an isolation structure over the substrate, and a fin over the substrate and adjacent to the isolation structure. The method further includes etching a portion of the fin, resulting in a trench, forming a doped material layer over bottom and sidewalls of the trench, and growing at least one epitaxial layer over the doped material layer in the trench. The method further includes recessing the isolation structure and the doped material layer, leaving a first portion of the at least one epitaxial layer surrounded by the doped material layer and performing an annealing process, thereby driving dopants from the doped material layer into the first portion.
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fullrecord <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_US2021020634A1</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>US2021020634A1</sourcerecordid><originalsourceid>FETCH-epo_espacenet_US2021020634A13</originalsourceid><addsrcrecordid>eNrjZFD3dQ3x8HdRcPRzUQgOCQp1DgkNclVw8w9ScPP0c3MNUXBxDfN0dg3mYWBNS8wpTuWF0twMykBZZw_d1IL8-NTigsTk1LzUkvjQYCMDI0MDIwMzYxNHQ2PiVAEAafgklQ</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>METHOD AND STRUCTURE FOR FINFET DEVICES</title><source>esp@cenet</source><creator>Chen, Hou-Yu ; Lu, Yong-Yan ; Soong, Chia-Wei</creator><creatorcontrib>Chen, Hou-Yu ; Lu, Yong-Yan ; Soong, Chia-Wei</creatorcontrib><description>A method for forming a semiconductor device comprises receiving a structure having a substrate, an isolation structure over the substrate, and a fin over the substrate and adjacent to the isolation structure. The method further includes etching a portion of the fin, resulting in a trench, forming a doped material layer over bottom and sidewalls of the trench, and growing at least one epitaxial layer over the doped material layer in the trench. The method further includes recessing the isolation structure and the doped material layer, leaving a first portion of the at least one epitaxial layer surrounded by the doped material layer and performing an annealing process, thereby driving dopants from the doped material layer into the first portion.</description><language>eng</language><subject>BASIC ELECTRIC ELEMENTS ; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ; ELECTRICITY ; SEMICONDUCTOR DEVICES</subject><creationdate>2021</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=20210121&amp;DB=EPODOC&amp;CC=US&amp;NR=2021020634A1$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,780,885,25564,76547</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=20210121&amp;DB=EPODOC&amp;CC=US&amp;NR=2021020634A1$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>Chen, Hou-Yu</creatorcontrib><creatorcontrib>Lu, Yong-Yan</creatorcontrib><creatorcontrib>Soong, Chia-Wei</creatorcontrib><title>METHOD AND STRUCTURE FOR FINFET DEVICES</title><description>A method for forming a semiconductor device comprises receiving a structure having a substrate, an isolation structure over the substrate, and a fin over the substrate and adjacent to the isolation structure. The method further includes etching a portion of the fin, resulting in a trench, forming a doped material layer over bottom and sidewalls of the trench, and growing at least one epitaxial layer over the doped material layer in the trench. The method further includes recessing the isolation structure and the doped material layer, leaving a first portion of the at least one epitaxial layer surrounded by the doped material layer and performing an annealing process, thereby driving dopants from the doped material layer into the first portion.</description><subject>BASIC ELECTRIC ELEMENTS</subject><subject>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</subject><subject>ELECTRICITY</subject><subject>SEMICONDUCTOR DEVICES</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2021</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZFD3dQ3x8HdRcPRzUQgOCQp1DgkNclVw8w9ScPP0c3MNUXBxDfN0dg3mYWBNS8wpTuWF0twMykBZZw_d1IL8-NTigsTk1LzUkvjQYCMDI0MDIwMzYxNHQ2PiVAEAafgklQ</recordid><startdate>20210121</startdate><enddate>20210121</enddate><creator>Chen, Hou-Yu</creator><creator>Lu, Yong-Yan</creator><creator>Soong, Chia-Wei</creator><scope>EVB</scope></search><sort><creationdate>20210121</creationdate><title>METHOD AND STRUCTURE FOR FINFET DEVICES</title><author>Chen, Hou-Yu ; Lu, Yong-Yan ; Soong, Chia-Wei</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_US2021020634A13</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>2021</creationdate><topic>BASIC ELECTRIC ELEMENTS</topic><topic>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</topic><topic>ELECTRICITY</topic><topic>SEMICONDUCTOR DEVICES</topic><toplevel>online_resources</toplevel><creatorcontrib>Chen, Hou-Yu</creatorcontrib><creatorcontrib>Lu, Yong-Yan</creatorcontrib><creatorcontrib>Soong, Chia-Wei</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Chen, Hou-Yu</au><au>Lu, Yong-Yan</au><au>Soong, Chia-Wei</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>METHOD AND STRUCTURE FOR FINFET DEVICES</title><date>2021-01-21</date><risdate>2021</risdate><abstract>A method for forming a semiconductor device comprises receiving a structure having a substrate, an isolation structure over the substrate, and a fin over the substrate and adjacent to the isolation structure. The method further includes etching a portion of the fin, resulting in a trench, forming a doped material layer over bottom and sidewalls of the trench, and growing at least one epitaxial layer over the doped material layer in the trench. The method further includes recessing the isolation structure and the doped material layer, leaving a first portion of the at least one epitaxial layer surrounded by the doped material layer and performing an annealing process, thereby driving dopants from the doped material layer into the first portion.</abstract><oa>free_for_read</oa></addata></record>
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subjects BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
SEMICONDUCTOR DEVICES
title METHOD AND STRUCTURE FOR FINFET DEVICES
url https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-01-03T10%3A41%3A42IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-epo_EVB&rft_val_fmt=info:ofi/fmt:kev:mtx:patent&rft.genre=patent&rft.au=Chen,%20Hou-Yu&rft.date=2021-01-21&rft_id=info:doi/&rft_dat=%3Cepo_EVB%3EUS2021020634A1%3C/epo_EVB%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rfr_iscdi=true