PACKAGE STRUCTURE AND METHOD FOR FORMING THE SAME
A package structure and a method for forming the same are provided. The package structure includes a die, a first molding surrounding the die, a first redistribution layer (RDL), an interposer disposed over the first RDL, a second molding surrounding the interposer, a first via, and a second RDL. Th...
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creator | CHIEN, CHIN-HER LIN, KAI-YUN LIU, CHINOU CHENG, YI-KAN TSAI, MING-KE HUANG, CHIN-YUAN WANG, TAI-YU TSAI, YAO-HSIEN LIU, KAI-MING HUANG, PO-HSIANG CHANG, FONG-YUAN YEH, CHENG-HUNG |
description | A package structure and a method for forming the same are provided. The package structure includes a die, a first molding surrounding the die, a first redistribution layer (RDL), an interposer disposed over the first RDL, a second molding surrounding the interposer, a first via, and a second RDL. The first RDL includes a first dielectric layer disposed over the die and the first molding, and a first interconnect structure surrounded by the first dielectric layer and electrically connected to the die. The interposer is electrically connected to the die through the first interconnect structure. The first via extends through and within the second molding and is adjacent to the interposer. The second RDL includes a second dielectric layer disposed over the interposer and the second molding, and a second interconnect structure surrounded by the second dielectric layer and electrically connected to the via and the interposer. |
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fullrecord | <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_US2020395281A1</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>US2020395281A1</sourcerecordid><originalsourceid>FETCH-epo_espacenet_US2020395281A13</originalsourceid><addsrcrecordid>eNrjZDAMcHT2dnR3VQgOCQp1DgkNclVw9HNR8HUN8fB3UXDzDwJhX08_d4UQD6AiR19XHgbWtMSc4lReKM3NoOzmGuLsoZtakB-fWlyQmJyal1oSHxpsZGBkYGxpamRh6GhoTJwqANPFJz0</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>PACKAGE STRUCTURE AND METHOD FOR FORMING THE SAME</title><source>esp@cenet</source><creator>CHIEN, CHIN-HER ; LIN, KAI-YUN ; LIU, CHINOU ; CHENG, YI-KAN ; TSAI, MING-KE ; HUANG, CHIN-YUAN ; WANG, TAI-YU ; TSAI, YAO-HSIEN ; LIU, KAI-MING ; HUANG, PO-HSIANG ; CHANG, FONG-YUAN ; YEH, CHENG-HUNG</creator><creatorcontrib>CHIEN, CHIN-HER ; LIN, KAI-YUN ; LIU, CHINOU ; CHENG, YI-KAN ; TSAI, MING-KE ; HUANG, CHIN-YUAN ; WANG, TAI-YU ; TSAI, YAO-HSIEN ; LIU, KAI-MING ; HUANG, PO-HSIANG ; CHANG, FONG-YUAN ; YEH, CHENG-HUNG</creatorcontrib><description>A package structure and a method for forming the same are provided. The package structure includes a die, a first molding surrounding the die, a first redistribution layer (RDL), an interposer disposed over the first RDL, a second molding surrounding the interposer, a first via, and a second RDL. The first RDL includes a first dielectric layer disposed over the die and the first molding, and a first interconnect structure surrounded by the first dielectric layer and electrically connected to the die. The interposer is electrically connected to the die through the first interconnect structure. The first via extends through and within the second molding and is adjacent to the interposer. The second RDL includes a second dielectric layer disposed over the interposer and the second molding, and a second interconnect structure surrounded by the second dielectric layer and electrically connected to the via and the interposer.</description><language>eng</language><subject>BASIC ELECTRIC ELEMENTS ; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ; ELECTRICITY ; SEMICONDUCTOR DEVICES</subject><creationdate>2020</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20201217&DB=EPODOC&CC=US&NR=2020395281A1$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,776,881,25542,76290</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20201217&DB=EPODOC&CC=US&NR=2020395281A1$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>CHIEN, CHIN-HER</creatorcontrib><creatorcontrib>LIN, KAI-YUN</creatorcontrib><creatorcontrib>LIU, CHINOU</creatorcontrib><creatorcontrib>CHENG, YI-KAN</creatorcontrib><creatorcontrib>TSAI, MING-KE</creatorcontrib><creatorcontrib>HUANG, CHIN-YUAN</creatorcontrib><creatorcontrib>WANG, TAI-YU</creatorcontrib><creatorcontrib>TSAI, YAO-HSIEN</creatorcontrib><creatorcontrib>LIU, KAI-MING</creatorcontrib><creatorcontrib>HUANG, PO-HSIANG</creatorcontrib><creatorcontrib>CHANG, FONG-YUAN</creatorcontrib><creatorcontrib>YEH, CHENG-HUNG</creatorcontrib><title>PACKAGE STRUCTURE AND METHOD FOR FORMING THE SAME</title><description>A package structure and a method for forming the same are provided. The package structure includes a die, a first molding surrounding the die, a first redistribution layer (RDL), an interposer disposed over the first RDL, a second molding surrounding the interposer, a first via, and a second RDL. The first RDL includes a first dielectric layer disposed over the die and the first molding, and a first interconnect structure surrounded by the first dielectric layer and electrically connected to the die. The interposer is electrically connected to the die through the first interconnect structure. The first via extends through and within the second molding and is adjacent to the interposer. The second RDL includes a second dielectric layer disposed over the interposer and the second molding, and a second interconnect structure surrounded by the second dielectric layer and electrically connected to the via and the interposer.</description><subject>BASIC ELECTRIC ELEMENTS</subject><subject>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</subject><subject>ELECTRICITY</subject><subject>SEMICONDUCTOR DEVICES</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2020</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZDAMcHT2dnR3VQgOCQp1DgkNclVw9HNR8HUN8fB3UXDzDwJhX08_d4UQD6AiR19XHgbWtMSc4lReKM3NoOzmGuLsoZtakB-fWlyQmJyal1oSHxpsZGBkYGxpamRh6GhoTJwqANPFJz0</recordid><startdate>20201217</startdate><enddate>20201217</enddate><creator>CHIEN, CHIN-HER</creator><creator>LIN, KAI-YUN</creator><creator>LIU, CHINOU</creator><creator>CHENG, YI-KAN</creator><creator>TSAI, MING-KE</creator><creator>HUANG, CHIN-YUAN</creator><creator>WANG, TAI-YU</creator><creator>TSAI, YAO-HSIEN</creator><creator>LIU, KAI-MING</creator><creator>HUANG, PO-HSIANG</creator><creator>CHANG, FONG-YUAN</creator><creator>YEH, CHENG-HUNG</creator><scope>EVB</scope></search><sort><creationdate>20201217</creationdate><title>PACKAGE STRUCTURE AND METHOD FOR FORMING THE SAME</title><author>CHIEN, CHIN-HER ; LIN, KAI-YUN ; LIU, CHINOU ; CHENG, YI-KAN ; TSAI, MING-KE ; HUANG, CHIN-YUAN ; WANG, TAI-YU ; TSAI, YAO-HSIEN ; LIU, KAI-MING ; HUANG, PO-HSIANG ; CHANG, FONG-YUAN ; YEH, CHENG-HUNG</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_US2020395281A13</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>2020</creationdate><topic>BASIC ELECTRIC ELEMENTS</topic><topic>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</topic><topic>ELECTRICITY</topic><topic>SEMICONDUCTOR DEVICES</topic><toplevel>online_resources</toplevel><creatorcontrib>CHIEN, CHIN-HER</creatorcontrib><creatorcontrib>LIN, KAI-YUN</creatorcontrib><creatorcontrib>LIU, CHINOU</creatorcontrib><creatorcontrib>CHENG, YI-KAN</creatorcontrib><creatorcontrib>TSAI, MING-KE</creatorcontrib><creatorcontrib>HUANG, CHIN-YUAN</creatorcontrib><creatorcontrib>WANG, TAI-YU</creatorcontrib><creatorcontrib>TSAI, YAO-HSIEN</creatorcontrib><creatorcontrib>LIU, KAI-MING</creatorcontrib><creatorcontrib>HUANG, PO-HSIANG</creatorcontrib><creatorcontrib>CHANG, FONG-YUAN</creatorcontrib><creatorcontrib>YEH, CHENG-HUNG</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>CHIEN, CHIN-HER</au><au>LIN, KAI-YUN</au><au>LIU, CHINOU</au><au>CHENG, YI-KAN</au><au>TSAI, MING-KE</au><au>HUANG, CHIN-YUAN</au><au>WANG, TAI-YU</au><au>TSAI, YAO-HSIEN</au><au>LIU, KAI-MING</au><au>HUANG, PO-HSIANG</au><au>CHANG, FONG-YUAN</au><au>YEH, CHENG-HUNG</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>PACKAGE STRUCTURE AND METHOD FOR FORMING THE SAME</title><date>2020-12-17</date><risdate>2020</risdate><abstract>A package structure and a method for forming the same are provided. The package structure includes a die, a first molding surrounding the die, a first redistribution layer (RDL), an interposer disposed over the first RDL, a second molding surrounding the interposer, a first via, and a second RDL. The first RDL includes a first dielectric layer disposed over the die and the first molding, and a first interconnect structure surrounded by the first dielectric layer and electrically connected to the die. The interposer is electrically connected to the die through the first interconnect structure. The first via extends through and within the second molding and is adjacent to the interposer. The second RDL includes a second dielectric layer disposed over the interposer and the second molding, and a second interconnect structure surrounded by the second dielectric layer and electrically connected to the via and the interposer.</abstract><oa>free_for_read</oa></addata></record> |
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subjects | BASIC ELECTRIC ELEMENTS ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ELECTRICITY SEMICONDUCTOR DEVICES |
title | PACKAGE STRUCTURE AND METHOD FOR FORMING THE SAME |
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