INSTRUCTION SUBSET IMPLEMENTATION FOR LOW POWER OPERATION

INSTRUCTION SUBSET IMPLEMENTATION FOR LOW POWER OPERATION

A heterogeneous processor system includes a first processor implementing an instruction set architecture (ISA) including a set of ISA features and configured to support a first subset of the set of ISA features. The heterogeneous processor system also includes a second processor implementing the ISA...

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Hauptverfasser: MEDNICK, Elliot H, MCLELLAN, Edward
Format: Patent
Sprache:eng
Schlagworte:
CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
PHYSICS
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creator MEDNICK, Elliot H
MCLELLAN, Edward
description A heterogeneous processor system includes a first processor implementing an instruction set architecture (ISA) including a set of ISA features and configured to support a first subset of the set of ISA features. The heterogeneous processor system also includes a second processor implementing the ISA including the set of ISA features and configured to support a second subset of the set of ISA features, wherein the first subset and the second subset of the set of ISA features are different from each other. When the first subset includes an entirety of the set of ISA features, the lower-feature second processor is configured to execute an instruction thread by consuming less power and with lower performance than the first processor.
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subjects CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
PHYSICS
title INSTRUCTION SUBSET IMPLEMENTATION FOR LOW POWER OPERATION
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