Time-limited debug mode

Time-limited debug mode

Embodiments of the present invention include an apparatus including a debug interface, a counter, and debug-enabling circuitry. The debug-enabling circuitry is configured to receive a debug-enabling input, and responsively to the debug-enabling input, enable the debug interface and start the counter...

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1. Verfasser: Kirschner, Yuval
Format: Patent
Sprache:eng
Schlagworte:
MEASURING
MEASURING ELECTRIC VARIABLES
MEASURING MAGNETIC VARIABLES
PHYSICS
TESTING
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creator Kirschner, Yuval
description Embodiments of the present invention include an apparatus including a debug interface, a counter, and debug-enabling circuitry. The debug-enabling circuitry is configured to receive a debug-enabling input, and responsively to the debug-enabling input, enable the debug interface and start the counter. The counter is configured to output an output signal that causes the debug interface to become disabled, following a predetermined duration from a time at which the counter was started. Other embodiments are also described.
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subjects MEASURING
MEASURING ELECTRIC VARIABLES
MEASURING MAGNETIC VARIABLES
PHYSICS
TESTING
title Time-limited debug mode
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