ACCELERATION METHOD, APPARATUS AND SYSTEM ON CHIP

Provided are an acceleration method, an apparatus and a system on chip. The acceleration method includes: the accelerator receives N-th parameter information of an N-th layer from a controller, wherein M layer of the deep neural network correspond to M application specific integrated circuit in the accelerator, wherein M and N are positive integer, M≥2, 1≤N≤M, executes computation of the N-th layer according to the N-th parameter information, and transmits N-th computation result information of the N-th layer indicates that the computation of the N-th layer is completed, to the controller, wherein the computation result information comprises computation result of the N-th layer. Then a complete flexibility for ASIC implementations of hardware accelerator can be achieved, and any kind of DNN based algorithms can be supported, which improves the universality of the accelerator.