HARDWARE ACCELERATION USING A SELF-PROGRAMMABLE COPROCESSOR ARCHITECTURE

Hardware acceleration using a self-programmable coprocessor architecture may include determining that an instruction cache comprises an accelerable instruction sequence; instead of executing the accelerable instruction sequence, providing, to an accelerator block of an accelerator complex comprising...

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Bibliographische Detailangaben

Hauptverfasser:	GINN, JUSTIN, SAWAN, TONY E
Format:	Patent
Sprache:	eng
Schlagworte:	CALCULATING COMPUTING COUNTING ELECTRIC DIGITAL DATA PROCESSING PHYSICS
Online-Zugang:	Volltext bestellen
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