SEMICONDUCTOR PACKAGE AND METHOD OF MAKING

SEMICONDUCTOR PACKAGE AND METHOD OF MAKING

The present disclosure provides a substrate for an integrated circuit. The substrate includes a dielectric layer. The substrate further includes a plurality of conductive elements at least partially embedded within the dielectric layer and having a substantially smooth outer surface. The substrate f...

Ausführliche Beschreibung

Gespeichert in:
Bibliographische Detailangaben
Hauptverfasser: Nad, Suddhasattwa, Manepalli, Rahul N
Format: Patent
Sprache:eng
Schlagworte:
BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
SEMICONDUCTOR DEVICES
Online-Zugang:Volltext bestellen
Tags: Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
container_end_page
container_issue
container_start_page
container_title
container_volume
creator Nad, Suddhasattwa
Manepalli, Rahul N
description The present disclosure provides a substrate for an integrated circuit. The substrate includes a dielectric layer. The substrate further includes a plurality of conductive elements at least partially embedded within the dielectric layer and having a substantially smooth outer surface. The substrate further includes an interlayer disposed between the individual conductive elements and the dielectric layer. The interlayer has a first surface comprising a plurality of protrusions interlocked with the dielectric layer and a second surface adhered to the outer surface of the individual conductive elements.
format Patent
fullrecord <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_US2020273787A1</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>US2020273787A1</sourcerecordid><originalsourceid>FETCH-epo_espacenet_US2020273787A13</originalsourceid><addsrcrecordid>eNrjZNAKdvX1dPb3cwl1DvEPUghwdPZ2dHdVcPRzUfB1DfHwd1Hwd1PwdfT29HPnYWBNS8wpTuWF0twMym6uIc4euqkF-fGpxQWJyal5qSXxocFGBkBobmxuYe5oaEycKgDLriVc</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>SEMICONDUCTOR PACKAGE AND METHOD OF MAKING</title><source>esp@cenet</source><creator>Nad, Suddhasattwa ; Manepalli, Rahul N</creator><creatorcontrib>Nad, Suddhasattwa ; Manepalli, Rahul N</creatorcontrib><description>The present disclosure provides a substrate for an integrated circuit. The substrate includes a dielectric layer. The substrate further includes a plurality of conductive elements at least partially embedded within the dielectric layer and having a substantially smooth outer surface. The substrate further includes an interlayer disposed between the individual conductive elements and the dielectric layer. The interlayer has a first surface comprising a plurality of protrusions interlocked with the dielectric layer and a second surface adhered to the outer surface of the individual conductive elements.</description><language>eng</language><subject>BASIC ELECTRIC ELEMENTS ; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ; ELECTRICITY ; SEMICONDUCTOR DEVICES</subject><creationdate>2020</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=20200827&amp;DB=EPODOC&amp;CC=US&amp;NR=2020273787A1$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,776,881,25542,76289</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=20200827&amp;DB=EPODOC&amp;CC=US&amp;NR=2020273787A1$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>Nad, Suddhasattwa</creatorcontrib><creatorcontrib>Manepalli, Rahul N</creatorcontrib><title>SEMICONDUCTOR PACKAGE AND METHOD OF MAKING</title><description>The present disclosure provides a substrate for an integrated circuit. The substrate includes a dielectric layer. The substrate further includes a plurality of conductive elements at least partially embedded within the dielectric layer and having a substantially smooth outer surface. The substrate further includes an interlayer disposed between the individual conductive elements and the dielectric layer. The interlayer has a first surface comprising a plurality of protrusions interlocked with the dielectric layer and a second surface adhered to the outer surface of the individual conductive elements.</description><subject>BASIC ELECTRIC ELEMENTS</subject><subject>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</subject><subject>ELECTRICITY</subject><subject>SEMICONDUCTOR DEVICES</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2020</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZNAKdvX1dPb3cwl1DvEPUghwdPZ2dHdVcPRzUfB1DfHwd1Hwd1PwdfT29HPnYWBNS8wpTuWF0twMym6uIc4euqkF-fGpxQWJyal5qSXxocFGBkBobmxuYe5oaEycKgDLriVc</recordid><startdate>20200827</startdate><enddate>20200827</enddate><creator>Nad, Suddhasattwa</creator><creator>Manepalli, Rahul N</creator><scope>EVB</scope></search><sort><creationdate>20200827</creationdate><title>SEMICONDUCTOR PACKAGE AND METHOD OF MAKING</title><author>Nad, Suddhasattwa ; Manepalli, Rahul N</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_US2020273787A13</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>2020</creationdate><topic>BASIC ELECTRIC ELEMENTS</topic><topic>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</topic><topic>ELECTRICITY</topic><topic>SEMICONDUCTOR DEVICES</topic><toplevel>online_resources</toplevel><creatorcontrib>Nad, Suddhasattwa</creatorcontrib><creatorcontrib>Manepalli, Rahul N</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Nad, Suddhasattwa</au><au>Manepalli, Rahul N</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>SEMICONDUCTOR PACKAGE AND METHOD OF MAKING</title><date>2020-08-27</date><risdate>2020</risdate><abstract>The present disclosure provides a substrate for an integrated circuit. The substrate includes a dielectric layer. The substrate further includes a plurality of conductive elements at least partially embedded within the dielectric layer and having a substantially smooth outer surface. The substrate further includes an interlayer disposed between the individual conductive elements and the dielectric layer. The interlayer has a first surface comprising a plurality of protrusions interlocked with the dielectric layer and a second surface adhered to the outer surface of the individual conductive elements.</abstract><oa>free_for_read</oa></addata></record>
fulltext fulltext_linktorsrc
identifier
ispartof
issn
language eng
recordid cdi_epo_espacenet_US2020273787A1
source esp@cenet
subjects BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
SEMICONDUCTOR DEVICES
title SEMICONDUCTOR PACKAGE AND METHOD OF MAKING
url https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-02-07T17%3A27%3A30IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-epo_EVB&rft_val_fmt=info:ofi/fmt:kev:mtx:patent&rft.genre=patent&rft.au=Nad,%20Suddhasattwa&rft.date=2020-08-27&rft_id=info:doi/&rft_dat=%3Cepo_EVB%3EUS2020273787A1%3C/epo_EVB%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rfr_iscdi=true