LOW LATENCY INTER-CHIP COMMUNICATION MECHANISM IN MULTI-CHIP PROCESSING SYSTEM

Systems and methods of multi-chip processing with low latency and congestion. In a multi-chip processing system, each chip includes a plurality of clusters arranged in a mesh design. A respective interconnect controller is disposed at the end of each column. The column is linked to a corresponding r...

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Bibliographische Detailangaben

Hauptverfasser:	Asher, David, Dobbie, Brad, Akkawi, Isam, Dever, Daniel, Kessler, Richard, Barner, Craig, Hummel, Tom
Format:	Patent
Sprache:	eng
Schlagworte:	CALCULATING COMPUTING COUNTING ELECTRIC DIGITAL DATA PROCESSING PHYSICS
Online-Zugang:	Volltext bestellen
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