Very Thin Embedded Trace Substrate-System in Package (SIP)

Very Thin Embedded Trace Substrate-System in Package (SIP)

A system in package is provided comprising an embedded trace substrate having redistribution layers therein, at least one passive component mounted on one side of the embedded trace substrate and embedded in a first molding compound, at least one silicon die mounted on an opposite side of the embedd...

Ausführliche Beschreibung

Gespeichert in:
Bibliographische Detailangaben
Hauptverfasser: Kent, Ian, Hu, Shou Cheng Eric, Aiyandra, Rajesh Subraya, Gutierrez, III, Ernesto, Belonio, JR., Jesus Mennen, Martin, Melvin
Format: Patent
Sprache:eng
Schlagworte:
BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
SEMICONDUCTOR DEVICES
Online-Zugang:Volltext bestellen
Tags: Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
container_end_page
container_issue
container_start_page
container_title
container_volume
creator Kent, Ian
Hu, Shou Cheng Eric
Aiyandra, Rajesh Subraya
Gutierrez, III, Ernesto
Belonio, JR., Jesus Mennen
Martin, Melvin
description A system in package is provided comprising an embedded trace substrate having redistribution layers therein, at least one passive component mounted on one side of the embedded trace substrate and embedded in a first molding compound, at least one silicon die mounted on an opposite side of the embedded trace substrate and embedded in a second molding compound wherein electrical connections are made between the at least one silicon die and the at least one passive component through the redistribution layers, and solder balls mounted through openings in the second molding layer to the redistribution layers wherein the solder balls provide package output.
format Patent
fullrecord <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_US2020227356A1</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>US2020227356A1</sourcerecordid><originalsourceid>FETCH-epo_espacenet_US2020227356A13</originalsourceid><addsrcrecordid>eNrjZLAKSy2qVAjJyMxTcM1NSk1JSU1RCClKTE5VCC5NKi4pSixJ1Q2uLC5JzVUAKglITM5OTE9V0Aj2DNDkYWBNS8wpTuWF0twMym6uIc4euqkF-fGpxQVAQ_JSS-JDg40MgNDI3NjUzNHQmDhVAH1ALlA</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>Very Thin Embedded Trace Substrate-System in Package (SIP)</title><source>esp@cenet</source><creator>Kent, Ian ; Hu, Shou Cheng Eric ; Aiyandra, Rajesh Subraya ; Gutierrez, III, Ernesto ; Belonio, JR., Jesus Mennen ; Martin, Melvin</creator><creatorcontrib>Kent, Ian ; Hu, Shou Cheng Eric ; Aiyandra, Rajesh Subraya ; Gutierrez, III, Ernesto ; Belonio, JR., Jesus Mennen ; Martin, Melvin</creatorcontrib><description>A system in package is provided comprising an embedded trace substrate having redistribution layers therein, at least one passive component mounted on one side of the embedded trace substrate and embedded in a first molding compound, at least one silicon die mounted on an opposite side of the embedded trace substrate and embedded in a second molding compound wherein electrical connections are made between the at least one silicon die and the at least one passive component through the redistribution layers, and solder balls mounted through openings in the second molding layer to the redistribution layers wherein the solder balls provide package output.</description><language>eng</language><subject>BASIC ELECTRIC ELEMENTS ; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ; ELECTRICITY ; SEMICONDUCTOR DEVICES</subject><creationdate>2020</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=20200716&amp;DB=EPODOC&amp;CC=US&amp;NR=2020227356A1$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,780,885,25564,76547</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=20200716&amp;DB=EPODOC&amp;CC=US&amp;NR=2020227356A1$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>Kent, Ian</creatorcontrib><creatorcontrib>Hu, Shou Cheng Eric</creatorcontrib><creatorcontrib>Aiyandra, Rajesh Subraya</creatorcontrib><creatorcontrib>Gutierrez, III, Ernesto</creatorcontrib><creatorcontrib>Belonio, JR., Jesus Mennen</creatorcontrib><creatorcontrib>Martin, Melvin</creatorcontrib><title>Very Thin Embedded Trace Substrate-System in Package (SIP)</title><description>A system in package is provided comprising an embedded trace substrate having redistribution layers therein, at least one passive component mounted on one side of the embedded trace substrate and embedded in a first molding compound, at least one silicon die mounted on an opposite side of the embedded trace substrate and embedded in a second molding compound wherein electrical connections are made between the at least one silicon die and the at least one passive component through the redistribution layers, and solder balls mounted through openings in the second molding layer to the redistribution layers wherein the solder balls provide package output.</description><subject>BASIC ELECTRIC ELEMENTS</subject><subject>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</subject><subject>ELECTRICITY</subject><subject>SEMICONDUCTOR DEVICES</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2020</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZLAKSy2qVAjJyMxTcM1NSk1JSU1RCClKTE5VCC5NKi4pSixJ1Q2uLC5JzVUAKglITM5OTE9V0Aj2DNDkYWBNS8wpTuWF0twMym6uIc4euqkF-fGpxQVAQ_JSS-JDg40MgNDI3NjUzNHQmDhVAH1ALlA</recordid><startdate>20200716</startdate><enddate>20200716</enddate><creator>Kent, Ian</creator><creator>Hu, Shou Cheng Eric</creator><creator>Aiyandra, Rajesh Subraya</creator><creator>Gutierrez, III, Ernesto</creator><creator>Belonio, JR., Jesus Mennen</creator><creator>Martin, Melvin</creator><scope>EVB</scope></search><sort><creationdate>20200716</creationdate><title>Very Thin Embedded Trace Substrate-System in Package (SIP)</title><author>Kent, Ian ; Hu, Shou Cheng Eric ; Aiyandra, Rajesh Subraya ; Gutierrez, III, Ernesto ; Belonio, JR., Jesus Mennen ; Martin, Melvin</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_US2020227356A13</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>2020</creationdate><topic>BASIC ELECTRIC ELEMENTS</topic><topic>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</topic><topic>ELECTRICITY</topic><topic>SEMICONDUCTOR DEVICES</topic><toplevel>online_resources</toplevel><creatorcontrib>Kent, Ian</creatorcontrib><creatorcontrib>Hu, Shou Cheng Eric</creatorcontrib><creatorcontrib>Aiyandra, Rajesh Subraya</creatorcontrib><creatorcontrib>Gutierrez, III, Ernesto</creatorcontrib><creatorcontrib>Belonio, JR., Jesus Mennen</creatorcontrib><creatorcontrib>Martin, Melvin</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Kent, Ian</au><au>Hu, Shou Cheng Eric</au><au>Aiyandra, Rajesh Subraya</au><au>Gutierrez, III, Ernesto</au><au>Belonio, JR., Jesus Mennen</au><au>Martin, Melvin</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>Very Thin Embedded Trace Substrate-System in Package (SIP)</title><date>2020-07-16</date><risdate>2020</risdate><abstract>A system in package is provided comprising an embedded trace substrate having redistribution layers therein, at least one passive component mounted on one side of the embedded trace substrate and embedded in a first molding compound, at least one silicon die mounted on an opposite side of the embedded trace substrate and embedded in a second molding compound wherein electrical connections are made between the at least one silicon die and the at least one passive component through the redistribution layers, and solder balls mounted through openings in the second molding layer to the redistribution layers wherein the solder balls provide package output.</abstract><oa>free_for_read</oa></addata></record>
fulltext fulltext_linktorsrc
identifier
ispartof
issn
language eng
recordid cdi_epo_espacenet_US2020227356A1
source esp@cenet
subjects BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
SEMICONDUCTOR DEVICES
title Very Thin Embedded Trace Substrate-System in Package (SIP)
url https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2024-12-22T20%3A35%3A26IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-epo_EVB&rft_val_fmt=info:ofi/fmt:kev:mtx:patent&rft.genre=patent&rft.au=Kent,%20Ian&rft.date=2020-07-16&rft_id=info:doi/&rft_dat=%3Cepo_EVB%3EUS2020227356A1%3C/epo_EVB%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rfr_iscdi=true