INTERRUPTIBLE TRANSLATION ENTRY INVALIDATION IN A MULTITHREADED DATA PROCESSING SYSTEM

A processor core among the plurality of processor cores initiates invalidation of translation entries buffered in the plurality of processor cores by executing a translation invalidation instruction in an initiating hardware thread. The processor core also executes, in the initiating hardware thread...

Ausführliche Beschreibung

Bibliographische Detailangaben

Hauptverfasser:	WILLIAMS, DEREK E, MAY, CATHY, HERRENSCHMIDT, BENJAMIN, FREY, BRADLY G
Format:	Patent
Sprache:	eng
Schlagworte:	CALCULATING COMPUTING COUNTING ELECTRIC DIGITAL DATA PROCESSING PHYSICS
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