Gate Structure and Method with Enhanced Gate Contact and Threshold Voltage

Gate Structure and Method with Enhanced Gate Contact and Threshold Voltage

The semiconductor structure includes a semiconductor substrate having a first region and a second region being adjacent to the first region; first fins formed on the semiconductor substrate within the first region; a first shallow trench isolation (STI) feature disposed on the semiconductor substrat...

Ausführliche Beschreibung

Gespeichert in:
Bibliographische Detailangaben
Hauptverfasser: Peng, Yen-Ming, Ho, Wei-Shuo, Liu, Max
Format: Patent
Sprache:eng
Schlagworte:
BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
SEMICONDUCTOR DEVICES
Online-Zugang:Volltext bestellen
Tags: Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
container_end_page
container_issue
container_start_page
container_title
container_volume
creator Peng, Yen-Ming
Ho, Wei-Shuo
Liu, Max
description The semiconductor structure includes a semiconductor substrate having a first region and a second region being adjacent to the first region; first fins formed on the semiconductor substrate within the first region; a first shallow trench isolation (STI) feature disposed on the semiconductor substrate within the second region; and a first gate stack that includes a first segment disposed directly on the first fins within the first region and a second segment extending to the first STI feature within the second region. The second segment of the first gate stack includes a low resistance metal (LRM) layer, a first tantalum titanium nitride layer, a titanium aluminum nitride layer, and a second tantalum titanium nitride layer stacked in sequence. The first segment of the first gate stack within the first region is free of the LRM layer.
format Patent
fullrecord <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_US2020144422A1</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>US2020144422A1</sourcerecordid><originalsourceid>FETCH-epo_espacenet_US2020144422A13</originalsourceid><addsrcrecordid>eNqNyjEKwjAUBuAsDqLe4YGz0MZcQEpVBKdW1_JI_hohJCV5xesLxQM4fcu3VrcLC6iTPFuZM4ijozvEJ0eft3hqo-do4Wh5TYrCVpbV-4ziU3D0TEH4ha1ajRwKdj83an9u--Z6wJQGlIktImR4dLrSVW2M0fpUH_9bX3vRNQY</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>Gate Structure and Method with Enhanced Gate Contact and Threshold Voltage</title><source>esp@cenet</source><creator>Peng, Yen-Ming ; Ho, Wei-Shuo ; Liu, Max</creator><creatorcontrib>Peng, Yen-Ming ; Ho, Wei-Shuo ; Liu, Max</creatorcontrib><description>The semiconductor structure includes a semiconductor substrate having a first region and a second region being adjacent to the first region; first fins formed on the semiconductor substrate within the first region; a first shallow trench isolation (STI) feature disposed on the semiconductor substrate within the second region; and a first gate stack that includes a first segment disposed directly on the first fins within the first region and a second segment extending to the first STI feature within the second region. The second segment of the first gate stack includes a low resistance metal (LRM) layer, a first tantalum titanium nitride layer, a titanium aluminum nitride layer, and a second tantalum titanium nitride layer stacked in sequence. The first segment of the first gate stack within the first region is free of the LRM layer.</description><language>eng</language><subject>BASIC ELECTRIC ELEMENTS ; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ; ELECTRICITY ; SEMICONDUCTOR DEVICES</subject><creationdate>2020</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=20200507&amp;DB=EPODOC&amp;CC=US&amp;NR=2020144422A1$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,780,885,25564,76547</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=20200507&amp;DB=EPODOC&amp;CC=US&amp;NR=2020144422A1$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>Peng, Yen-Ming</creatorcontrib><creatorcontrib>Ho, Wei-Shuo</creatorcontrib><creatorcontrib>Liu, Max</creatorcontrib><title>Gate Structure and Method with Enhanced Gate Contact and Threshold Voltage</title><description>The semiconductor structure includes a semiconductor substrate having a first region and a second region being adjacent to the first region; first fins formed on the semiconductor substrate within the first region; a first shallow trench isolation (STI) feature disposed on the semiconductor substrate within the second region; and a first gate stack that includes a first segment disposed directly on the first fins within the first region and a second segment extending to the first STI feature within the second region. The second segment of the first gate stack includes a low resistance metal (LRM) layer, a first tantalum titanium nitride layer, a titanium aluminum nitride layer, and a second tantalum titanium nitride layer stacked in sequence. The first segment of the first gate stack within the first region is free of the LRM layer.</description><subject>BASIC ELECTRIC ELEMENTS</subject><subject>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</subject><subject>ELECTRICITY</subject><subject>SEMICONDUCTOR DEVICES</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2020</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNqNyjEKwjAUBuAsDqLe4YGz0MZcQEpVBKdW1_JI_hohJCV5xesLxQM4fcu3VrcLC6iTPFuZM4ijozvEJ0eft3hqo-do4Wh5TYrCVpbV-4ziU3D0TEH4ha1ajRwKdj83an9u--Z6wJQGlIktImR4dLrSVW2M0fpUH_9bX3vRNQY</recordid><startdate>20200507</startdate><enddate>20200507</enddate><creator>Peng, Yen-Ming</creator><creator>Ho, Wei-Shuo</creator><creator>Liu, Max</creator><scope>EVB</scope></search><sort><creationdate>20200507</creationdate><title>Gate Structure and Method with Enhanced Gate Contact and Threshold Voltage</title><author>Peng, Yen-Ming ; Ho, Wei-Shuo ; Liu, Max</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_US2020144422A13</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>2020</creationdate><topic>BASIC ELECTRIC ELEMENTS</topic><topic>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</topic><topic>ELECTRICITY</topic><topic>SEMICONDUCTOR DEVICES</topic><toplevel>online_resources</toplevel><creatorcontrib>Peng, Yen-Ming</creatorcontrib><creatorcontrib>Ho, Wei-Shuo</creatorcontrib><creatorcontrib>Liu, Max</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Peng, Yen-Ming</au><au>Ho, Wei-Shuo</au><au>Liu, Max</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>Gate Structure and Method with Enhanced Gate Contact and Threshold Voltage</title><date>2020-05-07</date><risdate>2020</risdate><abstract>The semiconductor structure includes a semiconductor substrate having a first region and a second region being adjacent to the first region; first fins formed on the semiconductor substrate within the first region; a first shallow trench isolation (STI) feature disposed on the semiconductor substrate within the second region; and a first gate stack that includes a first segment disposed directly on the first fins within the first region and a second segment extending to the first STI feature within the second region. The second segment of the first gate stack includes a low resistance metal (LRM) layer, a first tantalum titanium nitride layer, a titanium aluminum nitride layer, and a second tantalum titanium nitride layer stacked in sequence. The first segment of the first gate stack within the first region is free of the LRM layer.</abstract><oa>free_for_read</oa></addata></record>
fulltext fulltext_linktorsrc
identifier
ispartof
issn
language eng
recordid cdi_epo_espacenet_US2020144422A1
source esp@cenet
subjects BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
SEMICONDUCTOR DEVICES
title Gate Structure and Method with Enhanced Gate Contact and Threshold Voltage
url https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2024-12-27T15%3A20%3A49IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-epo_EVB&rft_val_fmt=info:ofi/fmt:kev:mtx:patent&rft.genre=patent&rft.au=Peng,%20Yen-Ming&rft.date=2020-05-07&rft_id=info:doi/&rft_dat=%3Cepo_EVB%3EUS2020144422A1%3C/epo_EVB%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rfr_iscdi=true