Barrier for Power Metallization in Semiconductor Devices
A semiconductor device includes a structured interlayer on a substrate, a structured power metallization on the structured interlayer, and a barrier on the structured power metallization. The barrier is configured to prevent diffusion of at least one of water, water ions, sodium ions, potassium ions...
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| creator | Gatterbauer, Johann Goller, Klaus Albers, Katrin Mais, Norbert Busch, Joerg Kolitsch, Marianne Pelzer, Rainer Weidgans, Bernhard Nelhiebel, Michael |
| description | A semiconductor device includes a structured interlayer on a substrate, a structured power metallization on the structured interlayer, and a barrier on the structured power metallization. The barrier is configured to prevent diffusion of at least one of water, water ions, sodium ions, potassium ions, chloride ions, fluoride ions, and sulphur ions towards the structured power metallization. A first defined edge of the structured interlayer faces the same direction as a first defined edge of the structured power metallization and extends beyond the first defined edge of the structured power metallization by at least 0.5 microns. The structured interlayer has a compressive residual stress at room temperature and the structured power metallization generates a tensile stress at room temperature that is at least partly counteracted by the compressive residual stress of the structured interlayer. The first defined edge of the structured power metallization has a sidewall which slopes inward. |
| format | Patent |
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The first defined edge of the structured power metallization has a sidewall which slopes inward.</description><language>eng</language><subject>BASIC ELECTRIC ELEMENTS ; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ; ELECTRICITY ; MICROSTRUCTURAL DEVICES OR SYSTEMS, e.g. MICROMECHANICALDEVICES ; MICROSTRUCTURAL TECHNOLOGY ; PERFORMING OPERATIONS ; SEMICONDUCTOR DEVICES ; TRANSPORTING</subject><creationdate>2020</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20200409&DB=EPODOC&CC=US&NR=2020111754A1$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,780,885,25564,76547</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20200409&DB=EPODOC&CC=US&NR=2020111754A1$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>Gatterbauer, Johann</creatorcontrib><creatorcontrib>Goller, Klaus</creatorcontrib><creatorcontrib>Albers, Katrin</creatorcontrib><creatorcontrib>Mais, Norbert</creatorcontrib><creatorcontrib>Busch, Joerg</creatorcontrib><creatorcontrib>Kolitsch, Marianne</creatorcontrib><creatorcontrib>Pelzer, Rainer</creatorcontrib><creatorcontrib>Weidgans, Bernhard</creatorcontrib><creatorcontrib>Nelhiebel, Michael</creatorcontrib><title>Barrier for Power Metallization in Semiconductor Devices</title><description>A semiconductor device includes a structured interlayer on a substrate, a structured power metallization on the structured interlayer, and a barrier on the structured power metallization. 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| subjects | BASIC ELECTRIC ELEMENTS ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ELECTRICITY MICROSTRUCTURAL DEVICES OR SYSTEMS, e.g. MICROMECHANICALDEVICES MICROSTRUCTURAL TECHNOLOGY PERFORMING OPERATIONS SEMICONDUCTOR DEVICES TRANSPORTING |
| title | Barrier for Power Metallization in Semiconductor Devices |
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