METHOD FOR MANUFACTURING A PRESSURE SENSITIVE TRANSISTOR AND PRESSURE SENSITIVE FIELD EFFECT TRANSISTOR

A method for manufacturing a pressure sensitive transistor includes forming a channel region between first and second contact regions in a semiconductor substrate, forming a first isolation layer on a surface of the semiconductor substrate, forming a sacrificial structure on the first isolation laye...

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Hauptverfasser: Kautzsch, Thoralf, Komenko, Vladislav, Winkler, Bernhard, Froehlich, Heiko, Kravchenko, Andrey
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creator Kautzsch, Thoralf
Komenko, Vladislav
Winkler, Bernhard
Froehlich, Heiko
Kravchenko, Andrey
description A method for manufacturing a pressure sensitive transistor includes forming a channel region between first and second contact regions in a semiconductor substrate, forming a first isolation layer on a surface of the semiconductor substrate, forming a sacrificial structure on the first isolation layer and above the channel region, forming a semiconductor layer on the sacrificial structure and on the first isolation layer, wherein the semiconductor layer covers the sacrificial structure, removing the sacrificial structure for providing a cavity between the substrate and the semiconductor layer, wherein the semiconductor layer forms a membrane structure and forms a control electrode of the pressure sensitive transistor, forming a second isolation layer on the membrane structure and on the exposed portion of the surface of the semiconductor substrate, and forming contacting structures for the first contact region, the second contact region and the membrane structure of the pressure sensitive transistor.
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fullrecord <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_US2020105945A1</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>US2020105945A1</sourcerecordid><originalsourceid>FETCH-epo_espacenet_US2020105945A13</originalsourceid><addsrcrecordid>eNrjZEj3dQ3x8HdRcPMPUvB19At1c3QOCQ3y9HNXcFQICHINDg4NclUIdvUL9gzxDHNVCAlyBDKDQ4CqHf1csKlw83T1cVFwdXNzdQ5BUs7DwJqWmFOcyguluRmU3VxDnD10Uwvy41OLCxKTU_NSS-JDg40MjAwMDUwtTUwdDY2JUwUAIFk28w</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>METHOD FOR MANUFACTURING A PRESSURE SENSITIVE TRANSISTOR AND PRESSURE SENSITIVE FIELD EFFECT TRANSISTOR</title><source>esp@cenet</source><creator>Kautzsch, Thoralf ; Komenko, Vladislav ; Winkler, Bernhard ; Froehlich, Heiko ; Kravchenko, Andrey</creator><creatorcontrib>Kautzsch, Thoralf ; Komenko, Vladislav ; Winkler, Bernhard ; Froehlich, Heiko ; Kravchenko, Andrey</creatorcontrib><description>A method for manufacturing a pressure sensitive transistor includes forming a channel region between first and second contact regions in a semiconductor substrate, forming a first isolation layer on a surface of the semiconductor substrate, forming a sacrificial structure on the first isolation layer and above the channel region, forming a semiconductor layer on the sacrificial structure and on the first isolation layer, wherein the semiconductor layer covers the sacrificial structure, removing the sacrificial structure for providing a cavity between the substrate and the semiconductor layer, wherein the semiconductor layer forms a membrane structure and forms a control electrode of the pressure sensitive transistor, forming a second isolation layer on the membrane structure and on the exposed portion of the surface of the semiconductor substrate, and forming contacting structures for the first contact region, the second contact region and the membrane structure of the pressure sensitive transistor.</description><language>eng</language><subject>BASIC ELECTRIC ELEMENTS ; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ; ELECTRICITY ; SEMICONDUCTOR DEVICES</subject><creationdate>2020</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=20200402&amp;DB=EPODOC&amp;CC=US&amp;NR=2020105945A1$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,777,882,25545,76296</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=20200402&amp;DB=EPODOC&amp;CC=US&amp;NR=2020105945A1$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>Kautzsch, Thoralf</creatorcontrib><creatorcontrib>Komenko, Vladislav</creatorcontrib><creatorcontrib>Winkler, Bernhard</creatorcontrib><creatorcontrib>Froehlich, Heiko</creatorcontrib><creatorcontrib>Kravchenko, Andrey</creatorcontrib><title>METHOD FOR MANUFACTURING A PRESSURE SENSITIVE TRANSISTOR AND PRESSURE SENSITIVE FIELD EFFECT TRANSISTOR</title><description>A method for manufacturing a pressure sensitive transistor includes forming a channel region between first and second contact regions in a semiconductor substrate, forming a first isolation layer on a surface of the semiconductor substrate, forming a sacrificial structure on the first isolation layer and above the channel region, forming a semiconductor layer on the sacrificial structure and on the first isolation layer, wherein the semiconductor layer covers the sacrificial structure, removing the sacrificial structure for providing a cavity between the substrate and the semiconductor layer, wherein the semiconductor layer forms a membrane structure and forms a control electrode of the pressure sensitive transistor, forming a second isolation layer on the membrane structure and on the exposed portion of the surface of the semiconductor substrate, and forming contacting structures for the first contact region, the second contact region and the membrane structure of the pressure sensitive transistor.</description><subject>BASIC ELECTRIC ELEMENTS</subject><subject>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</subject><subject>ELECTRICITY</subject><subject>SEMICONDUCTOR DEVICES</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2020</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZEj3dQ3x8HdRcPMPUvB19At1c3QOCQ3y9HNXcFQICHINDg4NclUIdvUL9gzxDHNVCAlyBDKDQ4CqHf1csKlw83T1cVFwdXNzdQ5BUs7DwJqWmFOcyguluRmU3VxDnD10Uwvy41OLCxKTU_NSS-JDg40MjAwMDUwtTUwdDY2JUwUAIFk28w</recordid><startdate>20200402</startdate><enddate>20200402</enddate><creator>Kautzsch, Thoralf</creator><creator>Komenko, Vladislav</creator><creator>Winkler, Bernhard</creator><creator>Froehlich, Heiko</creator><creator>Kravchenko, Andrey</creator><scope>EVB</scope></search><sort><creationdate>20200402</creationdate><title>METHOD FOR MANUFACTURING A PRESSURE SENSITIVE TRANSISTOR AND PRESSURE SENSITIVE FIELD EFFECT TRANSISTOR</title><author>Kautzsch, Thoralf ; Komenko, Vladislav ; Winkler, Bernhard ; Froehlich, Heiko ; Kravchenko, Andrey</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_US2020105945A13</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>2020</creationdate><topic>BASIC ELECTRIC ELEMENTS</topic><topic>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</topic><topic>ELECTRICITY</topic><topic>SEMICONDUCTOR DEVICES</topic><toplevel>online_resources</toplevel><creatorcontrib>Kautzsch, Thoralf</creatorcontrib><creatorcontrib>Komenko, Vladislav</creatorcontrib><creatorcontrib>Winkler, Bernhard</creatorcontrib><creatorcontrib>Froehlich, Heiko</creatorcontrib><creatorcontrib>Kravchenko, Andrey</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Kautzsch, Thoralf</au><au>Komenko, Vladislav</au><au>Winkler, Bernhard</au><au>Froehlich, Heiko</au><au>Kravchenko, Andrey</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>METHOD FOR MANUFACTURING A PRESSURE SENSITIVE TRANSISTOR AND PRESSURE SENSITIVE FIELD EFFECT TRANSISTOR</title><date>2020-04-02</date><risdate>2020</risdate><abstract>A method for manufacturing a pressure sensitive transistor includes forming a channel region between first and second contact regions in a semiconductor substrate, forming a first isolation layer on a surface of the semiconductor substrate, forming a sacrificial structure on the first isolation layer and above the channel region, forming a semiconductor layer on the sacrificial structure and on the first isolation layer, wherein the semiconductor layer covers the sacrificial structure, removing the sacrificial structure for providing a cavity between the substrate and the semiconductor layer, wherein the semiconductor layer forms a membrane structure and forms a control electrode of the pressure sensitive transistor, forming a second isolation layer on the membrane structure and on the exposed portion of the surface of the semiconductor substrate, and forming contacting structures for the first contact region, the second contact region and the membrane structure of the pressure sensitive transistor.</abstract><oa>free_for_read</oa></addata></record>
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subjects BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
SEMICONDUCTOR DEVICES
title METHOD FOR MANUFACTURING A PRESSURE SENSITIVE TRANSISTOR AND PRESSURE SENSITIVE FIELD EFFECT TRANSISTOR
url https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-01-17T22%3A16%3A58IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-epo_EVB&rft_val_fmt=info:ofi/fmt:kev:mtx:patent&rft.genre=patent&rft.au=Kautzsch,%20Thoralf&rft.date=2020-04-02&rft_id=info:doi/&rft_dat=%3Cepo_EVB%3EUS2020105945A1%3C/epo_EVB%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rfr_iscdi=true