WAFER-LEVEL SYSTEM-IN-PACKAGE PACKAGING METHOD AND PACKAGE STRUCTURE THEREOF
Wafer-level system-in-package packaging method and package structure are provided. The method includes: forming a bonding structure, where the bonding structure includes a device wafer and a plurality of chips bonded to the device wafer, where the plurality of chips contains one or more first chips...
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Format: | Patent |
Sprache: | eng |
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Zusammenfassung: | Wafer-level system-in-package packaging method and package structure are provided. The method includes: forming a bonding structure, where the bonding structure includes a device wafer and a plurality of chips bonded to the device wafer, where the plurality of chips contains one or more first chips to-be-shielded; forming an encapsulation layer covering the plurality of chips; forming a trench in the encapsulation layer to surround each first chip of the one or more first chips; and forming a conductive material in the trench and on the encapsulation layer, where the conductive material includes a shielding housing, the shielding housing including a conductive sidewall formed in the trench and a conductive layer formed on a portion of the encapsulation layer above the each first chip and connected with the conductive sidewall. |
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