METHOD FOR POLISHING A SEMICONDUCTOR WAFER ON BOTH SIDES
Semiconductor wafers are polished on both sides between polishing pads of a Shore A hardness of at least 80 and a compressibility of less than 3%, attached to upper and lower polishing plates, the polishing pads attached to the upper and lower polishing plates by bonding the polishing pads to the pl...
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creator | DUTSCHKE, Vladimir |
description | Semiconductor wafers are polished on both sides between polishing pads of a Shore A hardness of at least 80 and a compressibility of less than 3%, attached to upper and lower polishing plates, the polishing pads attached to the upper and lower polishing plates by bonding the polishing pads to the plates, and positioning an intermediate pad having a compressibility of at least 3% between the two bonded polishing pads as an intermediate layer and then pressing together the two polishing pads with the intermediate pad situated therebetween for a period of time. |
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DRESSING OR CONDITIONING OF ABRADING SURFACES ; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ; ELECTRICITY ; FEEDING OF GRINDING, POLISHING, OR LAPPING AGENTS ; GRINDING ; MACHINES, DEVICES, OR PROCESSES FOR GRINDING OR POLISHING ; PERFORMING OPERATIONS ; POLISHING ; SEMICONDUCTOR DEVICES ; TRANSPORTING</subject><creationdate>2020</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20200206&DB=EPODOC&CC=US&NR=2020039020A1$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,776,881,25542,76290</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20200206&DB=EPODOC&CC=US&NR=2020039020A1$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>DUTSCHKE, Vladimir</creatorcontrib><title>METHOD FOR POLISHING A SEMICONDUCTOR WAFER ON BOTH SIDES</title><description>Semiconductor wafers are polished on both sides between polishing pads of a Shore A hardness of at least 80 and a compressibility of less than 3%, attached to upper and lower polishing plates, the polishing pads attached to the upper and lower polishing plates by bonding the polishing pads to the plates, and positioning an intermediate pad having a compressibility of at least 3% between the two bonded polishing pads as an intermediate layer and then pressing together the two polishing pads with the intermediate pad situated therebetween for a period of time.</description><subject>BASIC ELECTRIC ELEMENTS</subject><subject>DRESSING OR CONDITIONING OF ABRADING SURFACES</subject><subject>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</subject><subject>ELECTRICITY</subject><subject>FEEDING OF GRINDING, POLISHING, OR LAPPING AGENTS</subject><subject>GRINDING</subject><subject>MACHINES, DEVICES, OR PROCESSES FOR GRINDING OR POLISHING</subject><subject>PERFORMING OPERATIONS</subject><subject>POLISHING</subject><subject>SEMICONDUCTOR DEVICES</subject><subject>TRANSPORTING</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2020</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZLDwdQ3x8HdRcPMPUgjw9_EM9vD0c1dwVAh29fV09vdzCXUOAcqEO7q5Bin4-yk4-Yd4KAR7urgG8zCwpiXmFKfyQmluBmU31xBnD93Ugvz41OKCxOTUvNSS-NBgIwMjAwNjSyDpaGhMnCoA8ekpIw</recordid><startdate>20200206</startdate><enddate>20200206</enddate><creator>DUTSCHKE, Vladimir</creator><scope>EVB</scope></search><sort><creationdate>20200206</creationdate><title>METHOD FOR POLISHING A SEMICONDUCTOR WAFER ON BOTH SIDES</title><author>DUTSCHKE, Vladimir</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_US2020039020A13</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>2020</creationdate><topic>BASIC ELECTRIC ELEMENTS</topic><topic>DRESSING OR CONDITIONING OF ABRADING SURFACES</topic><topic>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</topic><topic>ELECTRICITY</topic><topic>FEEDING OF GRINDING, POLISHING, OR LAPPING AGENTS</topic><topic>GRINDING</topic><topic>MACHINES, DEVICES, OR PROCESSES FOR GRINDING OR POLISHING</topic><topic>PERFORMING OPERATIONS</topic><topic>POLISHING</topic><topic>SEMICONDUCTOR DEVICES</topic><topic>TRANSPORTING</topic><toplevel>online_resources</toplevel><creatorcontrib>DUTSCHKE, Vladimir</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>DUTSCHKE, Vladimir</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>METHOD FOR POLISHING A SEMICONDUCTOR WAFER ON BOTH SIDES</title><date>2020-02-06</date><risdate>2020</risdate><abstract>Semiconductor wafers are polished on both sides between polishing pads of a Shore A hardness of at least 80 and a compressibility of less than 3%, attached to upper and lower polishing plates, the polishing pads attached to the upper and lower polishing plates by bonding the polishing pads to the plates, and positioning an intermediate pad having a compressibility of at least 3% between the two bonded polishing pads as an intermediate layer and then pressing together the two polishing pads with the intermediate pad situated therebetween for a period of time.</abstract><oa>free_for_read</oa></addata></record> |
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subjects | BASIC ELECTRIC ELEMENTS DRESSING OR CONDITIONING OF ABRADING SURFACES ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ELECTRICITY FEEDING OF GRINDING, POLISHING, OR LAPPING AGENTS GRINDING MACHINES, DEVICES, OR PROCESSES FOR GRINDING OR POLISHING PERFORMING OPERATIONS POLISHING SEMICONDUCTOR DEVICES TRANSPORTING |
title | METHOD FOR POLISHING A SEMICONDUCTOR WAFER ON BOTH SIDES |
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